Low-stress passivation layer
Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
1 . A method of fabricating a semiconductor device, comprising:
receiving a workpiece that includes a redistribution layer disposed over and electrically coupled to an interconnect structure;
patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, wherein corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess, and wherein the patterning the redistribution layer includes an etching process that provides a rounding of the corners of the first conductive feature and the second conductive feature;
depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess;
depositing a nitride layer over the first dielectric layer; and
removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
2 . The method of claim 1 , wherein the etching process includes a first etching step and a second etching step, wherein the first etching step is performed using a first Cl 2 /BCl 3 gas ratio, and wherein the second etching step is performed using a second Cl 2 /BCl 3 gas ratio different than the first Cl 2 /BCl 3 gas ratio.
3 . The method of claim 2 , wherein the first Cl 2 /BCl 3 gas ratio is less than about 2, and wherein the second Cl 2 /BCl 3 gas ratio is in a range between about 2 and about 3.
4 . The method of claim 1 , further comprising:
after the patterning the redistribution layer and prior to depositing the first dielectric layer, performing an argon ion bombardment step primarily directed at the corners of the first conductive feature and the second conductive feature to provide an additional rounding of the corners of the first conductive feature and the second conductive feature.
5 . The method of claim 4 , wherein the argon ion bombardment is performed for a duration of time that is determined based on a pattern density of the redistribution layer.
6 . The method of claim 1 , wherein the removing the portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature is performed as part of depositing a second dielectric layer over the nitride layer.
7 . The method of claim 6 , wherein the depositing the second dielectric layer includes depositing the second dielectric layer using a high-density plasma chemical vapor deposition (HDPCVD) process.
8 . The method of claim 7 , wherein the HDPCVD process includes alternating deposition and etching-back cycles performed at different bias values and at different pressure.
9 . The method of claim 6 , wherein the first dielectric layer and the second dielectric layer are deposited using different deposition techniques.
10 . The method of claim 1 , wherein the depositing the first dielectric layer forms overhang regions at the corners of the first conductive feature and the second conductive feature due to an accumulation of the first dielectric layer.
11 . A method, comprising:
providing a substrate including a redistribution layer disposed over a multi-layer interconnect (MLI) structure;
depositing a nitride layer over the redistribution layer; and
forming a recess extending through the nitride layer and the redistribution layer, wherein the recess separates a first portion of the redistribution layer from a second portion of the redistribution layer, and wherein the forming the recess includes an etching process that provides a rounding of a corner of at least one of the first portion of the redistribution layer and the second portion of the redistribution layer on either side of the recess;
wherein after forming the recess, the nitride layer remains disposed over top surfaces of the first portion of the redistribution layer and the second portion of the redistribution layer, while sidewall surfaces of the first portion of the redistribution layer and the second portion of the redistribution layer are free of the nitride layer.
12 . The method of claim 11 , further comprising:
prior to depositing the nitride layer, depositing a first dielectric layer over the redistribution layer;
depositing the nitride layer over the first dielectric layer; and
forming the recess extending through the nitride layer, the first dielectric layer, and the redistribution layer.
13 . The method of claim 11 , wherein the forming the recess includes the etching process that further provides the rounding of corners of both the first portion of the redistribution layer and the second portion of the redistribution layer on either side of the recess.
14 . The method of claim 11 , wherein the etching process includes a first etching step and a second etching step, wherein the first etching step is performed using a first Cl 2 /BCl 3 gas ratio, and wherein the second etching step is performed using a second Cl 2 /BCl 3 gas ratio different than the first Cl 2 /BCl 3 gas ratio.
15 . The method of claim 14 , wherein the first Cl 2 /BCl 3 gas ratio is less than the second Cl 2 /BCl 3 gas ratio.
16 . The method of claim 13 , further comprising:
after forming the recess, performing an argon ion bombardment step primarily directed at the corners of the first portion of the redistribution layer and the second portion of the redistribution layer to provide an additional rounding of the corners of the first portion of the redistribution layer and the second portion of the redistribution layer.
17 . The method of claim 16 , wherein the argon ion bombardment is performed for a duration of time that is determined based on a pattern density of the redistribution layer.
18 . A semiconductor device, comprising:
a redistribution layer including a first conductive feature and a second conductive feature separated by a recess, wherein corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess;
a first passivation layer disposed over the redistribution layer and within the recess; and
a contact feature extending through the first passivation layer and electrically coupled to the first conductive feature;
wherein the first passivation layer includes a nitride layer having a discontinuity region that is substantially aligned with the corners of the first conductive feature and the second conductive feature, wherein the first passivation layer further includes a first dielectric layer interposing the redistribution layer and the nitride layer along upper sidewall portions of the recess and along top surfaces of the first and second conductive features, and wherein the first dielectric layer further interposes a second passivation layer underlying the redistribution layer and the nitride layer along lower sidewall portions of the recess and along a bottom surface of the recess; and
wherein a top surface of the first conductive feature defines a first plane, wherein a sidewall of the first conductive feature adjacent to the recess defines a second plane that intersects the first plane, and wherein a rounding of the corner of the first conductive feature is defined at least partly by a distance between the intersection of the first and second planes and a surface of the corner of the first conductive feature.
19 . The semiconductor device of claim 18 , wherein the first passivation layer further includes a second dielectric layer disposed over the nitride layer.
20 . The semiconductor device of claim 19 , wherein the first dielectric layer and the second dielectric layer are formed of different materials.