IP Library › Granted Patent US 12,622,287
Granted Patent B2
US 12,622,287 · App. 17/557,585 · Granted May 5, 2026

Multilayer glass substrate

Inventor: Telesphor Kamgaing (Chandler, AZ)
Assignee: Intel Corporation
H01L23/5383H01L23/291H01L24/05H01L2224/05008H01L2224/05188
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Quick Facts
Patent No.
US 12,622,287
App. No.
17/557,585
Granted
May 5, 2026
Kind
B2
Abstract

Embodiments herein relate to systems, apparatuses, techniques, or processes for packages that include multiple glass layers within the package. In embodiments, a core of the package may include multiple glass layers that may be bonded together, or may be separated by a dielectric layer between glass layers. In embodiments, the glass layers may include one or more electrically conductive features, such as conductive vias, conductive planes, electrical pads, electrical traces, redistribution layer, capacitors, inductors, active dies and/or passive dies. Other embodiments may be described and/or claimed.

Claims (43)

1 . A substrate comprising:

a first glass layer, wherein a first side of the first glass layer includes one or more electrically conductive features;

a second glass layer, wherein a side of the second glass layer includes one or more electrically conductive features;

wherein the first side of the first glass layer is coupled with the side of the second glass layer; and

a third glass layer coupled to a second side of the first glass layer, the second side of the glass layer opposite the first side of the first glass layer, wherein the third glass layer includes one or more electrically conductive features therein; and

a die coupled to the electrically conductive features in the third glass layer.

2 . The substrate of claim 1 , wherein the one or more electrically conductive features of the first glass layer or the one or more electrically conductive features of the second glass layer include a plurality of electrically conductive vias, wherein a pitch of the plurality of electrically conductive vias ranges from 50 μm to 100 μm.

3 . The substrate of claim 1 , wherein the first side of the first glass layer is electrically coupled with the side of the second glass layer.

4 . The substrate of claim 1 , wherein the one or more electrically conductive features include a selected one or more of: a conductive via, a conductive plane, an electrical pad, an electrical trace, a redistribution layer, a capacitor, an inductor, an active die, or a passive die.

5 . The substrate of claim 1 , wherein the first side of the first glass layer and the side of the second glass layer are directly coupled.

6 . The substrate of claim 5 , wherein the first side of the first glass layer and the side of the second glass layer are hybrid bonded.

7 . The substrate of claim 1 , wherein the first side of the first glass layer includes a cavity; and further including an electrical component within the cavity of the first glass layer.

8 . The substrate of claim 7 , wherein the electrical component within the cavity of the first glass layer is electrically coupled with the one or more electrically conductive features of the second glass layer.

9 . The substrate of claim 7 , wherein the electrical component within the cavity of the first glass layer is electrically coupled with a routing layer at a bottom of the cavity.

10 . The substrate of claim 7 , wherein the electrical component is a selected one of: an active component or a passive component.

11 . The substrate of claim 1 , wherein the first side of the first glass layer includes a first copper pad with a surface that is substantially parallel to a plane of the first side of the first glass layer, wherein the side of the second glass layer includes a second copper pad with a surface that is substantially parallel to the plane of the first side of the first glass layer, and wherein the first copper pad and the second copper pad at least partially overlap each other with respect to a direction perpendicular to the plane of the first side of the first glass layer; and

further comprising a dielectric layer between the first copper pad and the second copper pad, wherein the dielectric layer electrically isolates the first copper pad and the second copper pad from each other.

12 . The substrate of claim 1 , further comprising a dielectric layer between the first side of the first glass layer and the side of the second glass layer.

13 . The substrate of claim 12 , wherein the dielectric layer includes one or more electrically conductive features that electrically couple the first side of the first glass layer with the side of the second glass layer.

14 . The substrate of claim 11 , wherein the dielectric layer includes a capacitor, the capacitor comprising:

a first copper pad at a first side of the dielectric layer adjacent to the first glass layer;

a second copper pad at a second side of the dielectric layer adjacent to the second glass layer; and

wherein the first copper pad, the second copper pad, and a portion of the dielectric layer between the first copper pad and the second copper pad form the capacitor.

15 . The substrate of claim 1 , wherein the one or more electrically conductive features are formed using blind vias in the side of the first glass layer or in the side of the second glass layer.

16 . The substrate of claim 1 , wherein a side of the third glass layer includes one or more electrically conductive features; and

wherein the side of the third glass layer is electrically and physically coupled with the second side of the first glass layer.

17 . A substrate comprising:

a first glass layer, wherein a first side of the first glass layer includes one or more electrically conductive features;

a second glass layer, wherein a side of the second glass layer includes one or more electrically conductive features;

wherein the first side of the first glass layer is coupled with the side of the second glass layer;

a third glass layer coupled to a second side of the first glass layer, the second side of the glass layer opposite the first side of the first glass layer, wherein the first side of the first glass layer includes a first copper pad with a surface that is substantially parallel to a plane of the first side of the first glass layer, wherein the side of the second glass layer includes a second copper pad with a surface that is substantially parallel to the plane of the first side of the first glass layer, and wherein the first copper pad and the second copper pad at least partially overlap each other with respect to a direction perpendicular to the plane of the first side of the first glass layer; and

a dielectric layer between the first copper pad and the second copper pad, wherein the dielectric layer electrically isolates the first copper pad and the second copper pad from each other.

18 . The substrate of claim 17 , wherein the dielectric layer includes a capacitor, the capacitor comprising:

a first copper pad at a first side of the dielectric layer adjacent to the first glass layer;

a second copper pad at a second side of the dielectric layer adjacent to the second glass layer; and

wherein the first copper pad, the second copper pad, and a portion of the dielectric layer between the first copper pad and the second copper pad form the capacitor.

19 . A substrate comprising:

a first glass layer, wherein a first side of the first glass layer includes one or more electrically conductive features;

a second glass layer, wherein a side of the second glass layer includes one or more electrically conductive features;

wherein the first side of the first glass layer is coupled with the side of the second glass layer;

a third glass layer coupled to a second side of the first glass layer, the second side of the glass layer opposite the first side of the first glass layer; and

a dielectric layer between the first side of the first glass layer and the side of the second glass layer.

20 . The substrate of claim 19 , wherein the dielectric layer includes one or more electrically conductive features that electrically couple the first side of the first glass layer with the side of the second glass layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2022
From: KAMGAING, TELESPHOR
To: INTEL CORPORATION
Reel/Frame 061386/0741 →
Continuity (1)
Related Publication 20230197618A1 · Jun 22, 2023
References Cited (4)
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US 20200126906A1 · Uzoh · 2020 [cited by examiner]