Two-sided interconnected embedded chip packaging structure and manufacturing method therefor
A two-sided interconnected embedded chip packaging structure includes a first insulating layer and a second insulating layer. The first insulating layer includes a first conductive copper column layer penetrating through the first insulating layer in a height direction and a first chip located between adjacent first conductive copper columns, and the first chip is attached to the inside of the lower surface of the first insulating layer. The second insulating layer includes a first conductive wire layer and a heat radiation copper surface which are located in the upper surface of the second insulating layer, the first conductive wire layer is provided with a second conductive copper column layer, the first conductive copper column layer is connected with the first conductive wire layer, and the heat radiation copper surface is connected with the reverse side of the first chip.
1 . A two-sided interconnected embedded chip packaging structure, comprising:
a first insulating layer comprising a first conductive copper column layer penetrating through the first insulating layer in a height direction and a first chip located between adjacent first conductive copper columns, the first chip being attached to the inside of the lower surface of the first insulating layer; and
a second insulating layer comprising a first conductive wire layer and a heat radiation copper surface which are located in the upper surface of the second insulating layer, wherein the first insulating layer is laminated on the second insulating layer in a manner of contacting each other, the first conductive wire layer being provided with a second conductive copper column layer which penetrating through the second insulating layer, the first conductive copper column layer being connected with the first conductive wire layer, and the heat radiation copper surface being connected with the reverse side of the first chip; further comprising a device placing hole frame penetrating through the first insulating layer and the second insulating layer, wherein a second chip is attached to the bottom of the device placing hole frame, an insulated packaging layer is formed in a gap between the second chip and the device placing hole frame, and the first chip and the second chip differ in thickness;
wherein a second wire layer is disposed on the upper surface of the first insulating layer and a third wire layer is disposed on the lower surface of the second insulating layer, a terminal of the first chip is connected with the second wire layer, a terminal of the second chip is connected with the second wire layer or the third wire layer, the first conductive wire layer and the second wire layer are conducted and connected by the first conductive copper column layer, and the first conductive wire layer and the third wire layer are conducted and connected by the second conductive copper column layer.
2 . The two-sided interconnected embedded chip packaging structure of claim 1 , further comprising a first solder mask and a second solder mask respectively formed on the second wire layer and the third wire layer, a first metal surface treatment layer is disposed in the first solder mask, and a second metal surface treatment layer is disposed in the second solder mask.
3 . The two-sided interconnected embedded chip packaging structure of claim 1 , wherein each of the first chip and the second chip comprises at least one chip.
4 . The two-sided interconnected embedded chip packaging structure of claim 1 , wherein the first insulating layer and the second insulating layer comprise the same or different insulating materials.
5 . The two-sided interconnected embedded chip packaging structure of claim 1 , wherein an end of the first conductive copper column layer is flush with or higher than the first insulating layer, and an end of the second conductive copper column layer is flush with or higher than the second insulating layer.
6 . The two-sided interconnected embedded chip packaging structure of claim 1 , wherein each of the first conductive copper column layer and the second conductive copper column layer comprises at least one copper through hole column.
7 . The two-sided interconnected embedded chip packaging structure of claim 6 , wherein each of the first conductive copper column layer and the second conductive copper column layer comprises at least one copper through hole column with the same or different sectional sizes and/or shapes.