Waveguide transitions for hybrid thin-silicon/III-V photonics
A device comprises a substrate having lower and upper silicon layers separated by a lower dielectric layer and a III-V structure bonded to the substrate, with first, second, and third sections along an optical axis. The first section comprises a first upper waveguide segment of the upper silicon layer, increasing in width from a first width to a second width at an interface between the first and second sections, the III-V structure overlapping with a tapered portion of the first upper waveguide segment. The second section comprises a second upper waveguide segment of the upper silicon layer decreasing in width, and a first lower waveguide segment of the lower silicon layer wider than the second upper waveguide segment at the interface between the second and third sections. The third section comprises a second lower waveguide segment of the lower silicon layer.
1 . A device comprising:
a substrate comprising lower and upper silicon layers separated by a lower dielectric layer;
a III-V structure bonded to the substrate; and
formed in the substrate and the III-V structure, a waveguide transition structure comprising first, second, and third sections along an optical axis, wherein:
the first section comprises a first upper waveguide segment formed in the upper silicon layer, the first upper waveguide segment increasing in width from a first width to a second width at an interface between the first and second sections, the III-V structure overlapping with the first upper waveguide segment;
the second section comprises a second upper waveguide segment formed in the upper silicon layer and a first lower waveguide segment formed in the lower silicon layer, the second upper waveguide segment decreasing in width from the second width at the interface between the first and second sections to a third width at an interface between the second and third sections, the first lower waveguide segment decreasing in width from a fifth width at the interface between the first and second sections to a fourth width at the interface between the second and third sections, the fifth width being greater than the second width, the fourth width being greater than the third width; and
the third section comprises a second lower waveguide segment having the fourth width, formed in the lower silicon layer contiguously with the first lower waveguide segment.
2 . The device of claim 1 , wherein the first section further comprises a slab in the lower silicon layer.
3 . The device of claim 1 , wherein the first section further comprises a third lower waveguide segment that increases in width from the first width to the second width at the interface between the first and second sections, and wherein the first lower waveguide segment has the fourth width.
4 . The device of claim 1 , further comprising a top dielectric layer separating the III-V structure from the upper silicon layer.
5 . The device of claim 4 , wherein the top dielectric layer has a thickness less than 100 nm.
6 . The device of claim 1 , wherein the lower silicon layer and upper silicon layer each have a thickness between 100 nm and 300 nm.
7 . The device of claim 1 , wherein the III-V structure includes a curved portion angled away from the optical axis, the curved portion decoupling the III-V structure from the upper silicon layer in at least a portion of the second section.
8 . The device of claim 7 , wherein the curved portion of the III-V structure terminates in a light trapping structure.
9 . The device of claim 6 , wherein the lower silicon layer comprises an optical modulator comprising a doped p-n junction.
10 . The device of claim 1 , further comprising:
germanium formed on at least one of the lower silicon layer or the upper silicon layer; and
one or more photodetectors comprising the germanium and the at least one of the lower silicon layer or the upper silicon layer.
11 . The device of claim 1 , wherein the first width of the first upper waveguide segment is 0.3 μm or less, and the second width of the first upper waveguide segment is between 1 μm and 3 μm.
12 . The device of claim 1 , wherein the third width of the second upper waveguide segment is 0.5 μm or less.
13 . The device of claim 1 , wherein the fourth width of the second lower waveguide segment is between 0.5 μm and 3 μm.
14 . The device of claim 1 , wherein the third section is free of the upper silicon layer and the III-V structure.
15 . The device of claim 1 , wherein the III-V structure comprises a mesa-type p-i-n structure.
16 . The device of claim 15 , wherein the mesa-type p-i-n structure comprises:
a bottom layer of n-type III-V material;
a slab of optically active III-V material disposed above the bottom layer; and
a rib of p-type III-V material disposed above the slab, the rib of p-type III-V material being narrower than the slab of optically active III-V material.
17 . A method of manufacturing a photonic device, the method comprising:
providing a substrate comprising a lower silicon layer disposed on an insulating layer, the substrate comprising a first section, second section, and third section arranged sequentially along an optical axis of the photonic device;
forming an upper silicon layer over the lower silicon layer in the first and second sections with a lower dielectric layer separating the upper and lower silicon layers;
patterning the upper silicon layer to form:
a first upper waveguide segment in the first section, the first upper waveguide segment increasing in width from a first width to a second width at an interface between the first and second sections; and
a second upper waveguide segment in the second section, the second upper waveguide segment decreasing in width from the second width at the interface between the first and second sections to a third width at an interface between the second and third sections;
patterning the lower silicon layer to form:
a first lower waveguide segment in the second section decreasing in width from a fifth width at the interface between the first and second sections to a fourth width at the interface between the second and third sections, the fifth width being greater than the second width, the fourth width being greater than the third width; and
a second lower waveguide segment in the third section having the fourth width, formed in the lower silicon layer contiguously with the first lower waveguide segment;
forming a top dielectric layer above the upper silicon layer;
bonding a III-V semiconductor structure to the top dielectric layer in the first section; and
patterning the III-V semiconductor structure to form a III-V waveguide overlapping the first upper waveguide segment in the first section.
18 . The method of claim 17 ,
further comprising patterning the lower silicon layer to form a slab in the lower silicon layer in the first section.
19 . The method of claim 17 ,
further comprising patterning the lower silicon layer to form a third lower waveguide segment in the first section that increases in width from the first width to the second width at the interface between the first and second sections;
wherein the first lower waveguide segment has the fourth width.
20 . The method of claim 17 , further comprising:
forming germanium on at least one of the lower silicon layer or the upper silicon layer; and
forming one or more photodetectors comprising the germanium.