Memory, storage systems, and operation methods of memory

1 . A memory, comprising:

a plurality of memory planes; and

a peripheral circuit coupled to the plurality of memory planes, comprising:

a plurality of charge pumps, wherein each of the plurality of charge pumps has a clock signal end, an input end, and an output end, the output end of each of the plurality of charge pumps coupled to a memory plane of the plurality of memory planes, and each of the plurality of charge pumps is configured to boost an input voltage of the input end according to a first clock signal and a second clock signal received by the clock signal end and output the same to the output end, and wherein the first and second clock signals received by the clock signal ends of the plurality of charge pumps are different and there is a preset delay time between the first and second clock signals received by the clock signal ends;

a clock generator configured to generate the first clock signal; and

a clock processing circuit configured to delay the first clock signal with the preset delay time to generate the second clock signal different from the first clock signal based on the first clock signal.

2 . The memory of claim 1 , wherein the clock processing circuit includes an input end coupled to the clock generator.

3 . The memory of claim 1 , wherein the preset delay time is less than a clock cycle of the first clock signal.

4 . The memory of claim 1 , wherein the preset delay time is half of a clock cycle of the first clock signal.

5 . The memory of claim 1 , wherein the peripheral circuit further comprises a multiplexer coupled between the plurality of charge pumps and the plurality of memory planes,

wherein, in an async multi-plane independent read operation, each of the plurality of charge pumps is coupled to the memory plane of the plurality of memory planes through the multiplexer; and

in a normal read operation, the plurality of charge pumps are connected in parallel through the multiplexer, and output ends of the plurality of charge pumps are coupled to an output node jointly.

6 . The memory of claim 2 , wherein the plurality of charge pumps comprise:

a first charge pump group comprising at least one first charge pump;

a second charge pump group comprising at least one second charge pump,

wherein a number of first charge pumps in the first charge pump group is the same as a number of second charge pumps in the second charge pump group;

a clock signal generation circuit, including the clock generator and the clock processing circuit, comprises a first output end and a second output end;

the clock signal generation circuit is configured to provide a clock signal to a first clock signal end of the first charge pump through the first output end; and

the clock signal generation circuit is configured to provide the clock signal to a second clock signal end of the second charge pump through the second output end.

7 . The memory of claim 6 , wherein the first charge pump group is configured to, during a ramping stage, boost the input voltage received by a first input end of the first charge pump and output the same to an output node based on the first clock signal received by the first clock signal end; and

the second charge pump group is configured to, during the ramping stage, boost the input voltage received by a second input end of the second charge pump and output the same to the output node based on the second clock signal received by the second clock signal end.

8 . The memory of claim 7 , wherein any of the first charge pumps in the first charge pump group is configured to, during a stable stage and according to a third clock signal received by the first clock signal end, process the input voltage received by the first input end of the first charge pump and output the same to the output node; and

any of the second charge pumps in the second charge pump group is configured to, during the stable stage and according to a fourth clock signal received by the second clock signal end, process the input voltage received by the second input end of the second charge pump and then output the same to the output node.

9 . The memory of claim 8 , wherein the clock signal generation circuit further comprises:

a first selection switch; and

a first clock divider,

wherein an input end of the first selection switch is coupled to the clock generator, an output end of the first selection switch is coupled to the first output end of the clock signal generation circuit or to the first clock divider, and an output end of the first clock divider is coupled to the first output end of the clock signal generation circuit;

the first selection switch is configured so that, during the ramping stage, the output end of the first selection switch is coupled to the first output end of the clock signal generation circuit to transmit the first clock signal generated by the clock generator to the first charge pump, and, during the stable stage, the output end of the first selection switch is coupled to the first clock divider to transmit the first clock signal generated by the clock generator to the first clock divider; and

the first clock divider is configured to, during the stable stage, perform frequency division processing according to the first clock signal to generate the third clock signal and transmit the third clock signal to the first charge pump.

10 . The memory of claim 8 , wherein the clock signal generation circuit further comprises:

a second selection switch;

a second clock divider,

wherein an input end of the second selection switch is coupled to the clock processing circuit, an output end of the second selection switch is coupled to the second output end of the clock signal generation circuit or to the second clock divider, and an output end of the second clock divider is coupled to the second output end of the clock signal generation circuit;

the second selection switch is configured so that, during the ramping stage, the output end of the second selection switch is coupled to the second output end of the clock signal generation circuit to transmit the second clock signal generated by the clock processing circuit to the second charge pump, and, during the stable stage, the output end of the second selection switch is coupled to the second clock divider to transmit the second clock signal generated by the clock processing circuit to the second clock divider; and

the second clock divider is configured to, during the stable stage, perform frequency division processing according to the second clock signal to generate the fourth clock signal and transmit the fourth clock signal to the second charge pump.

11 . The memory of claim 8 , wherein a clock cycle of the first clock signal and a clock cycle of the second clock signal are both a first cycle, a clock cycle of the third clock signal and a clock cycle of the fourth clock signal are the same and are a second cycle, and wherein the second cycle is twice the first cycle.

12 . The memory of claim 2 , wherein the clock processing circuit further comprises an inverter circuit.

13 . The memory of claim 1 , wherein a charge pump of the plurality of charge pumps boosts the input voltage of the input end and then outputs an output voltage to the output end, and wherein an absolute value of the output voltage is greater than an absolute value of the input voltage.

14 . A memory system, comprising:

a memory, comprising:

a plurality of memory planes; and

a peripheral circuit coupled to the plurality of memory planes and comprising:

a plurality of charge pumps, wherein each of the plurality of charge pumps has a clock signal end, an input end, and an output end, the output end of each of the plurality of charge pumps is coupled to a memory plane of the plurality of memory planes, and each of the plurality of charge pumps is configured to boost an input voltage of the input end according to a clock signal received by the clock signal end and output the same to the output end, and wherein the clock signals received by clock signal ends of the plurality of charge pumps are different; and

a multiplexer coupled between the plurality of charge pumps and the plurality of memory planes, wherein, in an async multi-plane independent read operation, each of the plurality of charge pumps is coupled to the memory plane through the multiplexer, and, in a normal read operation, the plurality of charge pumps are connected in parallel through the multiplexer, and output ends of the plurality of charge pumps are coupled to an output node jointly; and

a controller coupled to the memory and configured to control the memory.

15 . An operation method of a memory, wherein the memory comprises a plurality of memory planes and a peripheral circuit coupled to the memory planes; the peripheral circuit comprises a plurality of charge pumps, a clock generator configured to generate a first clock signal, and a clock processing circuit configured to generate a second clock signal different from the first clock signal based on the first clock signal; a charge pump has a clock signal end, an input end, and an output end; and the output end of each of the charge pumps is coupled to one of the plurality of memory planes, and

the operation method comprises:

receiving, by clock signal ends of the plurality of charge pumps, the first and second clock signals;

boosting input voltages of the input ends and then outputting the same to the output ends, in response to the first and second clock signals received by the clock signal ends; and

delaying, by the clock processing circuit, the first clock signal with a preset delay time to generate the second clock signal, the preset delay time being a time between the first and second clock signals received by the clock signal ends.

16 . The operation method of claim 15 , wherein the clock processing circuit includes an input end coupled to the clock generator.

17 . The memory system of claim 14 , wherein the peripheral circuit further comprises a clock signal generation circuit comprising:

a clock generator configured to generate a first clock signal; and

a clock processing circuit including an input end coupled to the clock generator and configured to delay the first clock signal with a preset delay time to generate a second clock signal different from the first clock signal based on the first clock signal, wherein the preset delay time is a time between the first and second clock signals received by the clock signal ends.

18 . The memory system of claim 17 , wherein the preset delay time is less than a clock cycle of the first clock signal.

19 . The memory of claim 17 , wherein the preset delay time is half of a clock cycle of the first clock signal.

20 . The memory system of claim 17 , wherein the plurality of charge pumps comprise:

a first charge pump group comprising at least one first charge pump;

a second charge pump group comprising at least one second charge pump, wherein a number of first charge pumps in the first charge pump group is the same as a number of second charge pumps in the second charge pump group;

the clock signal generation circuit comprises a first output end and a second output end;

the clock signal generation circuit is configured to provide a clock signal to a first clock signal end of the first charge pump through the first output end; and

the clock signal generation circuit is configured to provide the clock signal to a second clock signal end of the second charge pump through the second output end.