Memory device structure and fabrication method

1 . A three-dimensional (3D) memory device, comprising:

an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a stair structure, wherein the memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one driver region; and

a CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region,

wherein the array wafer and the CMOS wafer are bonded at a bonding interface;

the bonding interface is between a CMOS joint layer of the CMOS wafer and an array joint layer of the array wafer; and

the CMOS joint layer of the CMOS wafer and the array joint layer of the array wafer are bonded, and one or more joint structures on the array joint layer of the array wafer and one or more joint structures on the CMOS joint layer of the CMOS wafer are bonded together for electrical connection, and

a vertical projection of the at least one page buffer region of the CMOS wafer fits within a vertical projection of the at least one cell region of the memory array layer.

2 . The 3D memory device according to claim 1 , wherein:

the CMOS wafer includes a plurality of page buffers formed in the at least one page buffer region, including HV circuits of the page buffers, and the at least one page buffer region corresponds to the at least one cell region; and

the CMOS layer includes a driver formed in the at least one driver region, and the driver region corresponds to the at least one stair structure region.

3 . A three-dimensional (3D) memory device, comprising:

an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a stair structure, wherein the memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one driver region; and

a CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region,

wherein the array wafer and the CMOS wafer are bonded at a bonding interface;

the CMOS wafer includes a plurality of page buffers formed in the at least one page buffer region, including HV circuits of the page buffers, and the at least one page buffer region corresponds to the at least one cell region;

the CMOS layer includes a driver formed in the at least one driver region, and the driver region corresponds to the at least one stair structure region;

the at least one cell region is a single center portion of the memory array layer, and the at least one stair structure region are two side portions of the memory array layer;

the at least one page buffer region is a single center portion of the CMOS wafer; and

the at least one driver region are two side portions of the CMOS layer.

4 . A three-dimensional (3D) memory device, comprising:

an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a stair structure, wherein the memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one driver region; and

a CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region,

wherein the array wafer and the CMOS wafer are bonded at a bonding interface;

the CMOS wafer includes a plurality of page buffers formed in the at least one page buffer region, including HV circuits of the page buffers, and the at least one page buffer region corresponds to the at least one cell region;

the CMOS layer includes a driver formed in the at least one driver region, and the driver region corresponds to the at least one stair structure region;

the at least one cell region are two side portions of the memory array layer, and the at least one stair structure region is a single center portion of the memory array layer;

the at least one page buffer region are two side portions of the CMOS wafer; and

the at least one driver region is a single center portion of the CMOS layer.

5 . The 3D memory device according to claim 2 , wherein the CMOS layer is formed based on a peripheral-under-chip (PUC) mechanism, and the CMOS layer is located under the memory array layer and separated by a base layer for forming the memory array layer.

6 . The 3D memory device according to claim 5 , wherein the base layer is a polysilicon layer, the array wafer includes a first substrate, the CMOS layer comprises a device layer formed on the first substrate, the polysilicon layer is formed on the device layer of the CMOS layer, and the memory array layer is formed on the polysilicon layer.

7 . The 3D memory device according to claim 6 , wherein the CMOS wafer includes a second substrate for forming HV circuits of the page buffers and the low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices.

8 . The 3D memory device according to claim 1 , wherein the 3D memory device further comprises:

an insulating layer formed over the second substrate;

at least one through substrate contact penetrating the second substrate; and

at least one array pad in contact with the at least one through substrate contact.

9 . The 3D memory device according to claim 3 , wherein the CMOS layer is formed based on a peripheral-under-chip (PUC) mechanism, and the CMOS layer is located under the memory array layer and separated by a base layer for forming the memory array layer.

10 . The 3D memory device according to claim 9 , wherein the base layer is a polysilicon layer, the array wafer includes a first substrate, the CMOS layer comprises a device layer formed on the first substrate, the polysilicon layer is formed on the device layer of the CMOS layer, and the memory array layer is formed on the polysilicon layer.

11 . The 3D memory device according to claim 10 , wherein the CMOS wafer includes a second substrate for forming HV circuits of the page buffers and the low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices.

12 . The 3D memory device according to claim 3 , wherein the 3D memory device further comprises:

an insulating layer formed over the second substrate;

at least one through substrate contact penetrating the second substrate; and

at least one array pad in contact with the at least one through substrate contact.

13 . The 3D memory device according to claim 4 , wherein the CMOS layer is formed based on a peripheral-under-chip (PUC) mechanism, and the CMOS layer is located under the memory array layer and separated by a base layer for forming the memory array layer.

14 . The 3D memory device according to claim 13 , wherein the base layer is a polysilicon layer, the array wafer includes a first substrate, the CMOS layer comprises a device layer formed on the first substrate, the polysilicon layer is formed on the device layer of the CMOS layer, and the memory array layer is formed on the polysilicon layer.

15 . The 3D memory device according to claim 14 , wherein the CMOS wafer includes a second substrate for forming HV circuits of the page buffers and the low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices.

16 . The 3D memory device according to claim 4 , wherein the 3D memory device further comprises:

an insulating layer formed over the second substrate;

at least one through substrate contact penetrating the second substrate; and

at least one array pad in contact with the at least one through substrate contact.