Three-dimensional flash memory having improved integration density
View Patent ↗The present invention relates to a three-dimension flash memory to which an efficient word line connection structure is applied, and a method for manufacturing same, wherein a plurality of word lines are connected to a low decoder respectively through contacts of the plurality of word lines, a plurality of connection wires, and plug vias of the plurality of word lines. The row decoder and a column decoder are arranged to divide a plurality of peripheral circuit blocks such that the plurality of peripheral circuit blocks are symmetrical to each other in the plane of the three-dimensional flash memory. The three-dimension flash memory is configured in a buried type in which a common source line is buried in a substrate, in order to improve integration density.
1 . A three-dimensional flash memory to which an efficient word line connection structure is applied, the three-dimensional flash memory comprising:
at least one memory cell string extending in one direction;
a plurality of word lines vertically connected to the at least one memory cell string; and
a row decoder located below the plurality of word lines,
wherein each of the plurality of word lines is connected to the row decoder through a plug via connected to a contact of each of the plurality of word lines,
wherein a plurality of connection wires connecting the plug via of each of the plurality of word lines to the contact of each of the plurality of word lines are arranged in a plane of the plurality of word lines,
wherein the plurality of connection wires include a vertical portion and a horizontal portion, and
wherein, on the plane of the plurality of word lines, a position of each plug via and a position of each contact are configured to minimize a length of the horizontal portion of each of the plurality of connection wires.
2 . The three-dimensional flash memory of claim 1 , wherein the plug via of each of the plurality of word lines passes through each of the plurality of word lines on a plane of the plurality of word lines and contacts the row decoder.
3 . The three-dimensional flash memory of claim 2 , wherein the plug via of each of the plurality of word lines has a structure that is isolated from each of the plurality of word lines on the plane.
4 . The three-dimensional flash memory of claim 3 , wherein the plug via of each of the plurality of word lines is isolated from each of the plurality of word lines on a plane by an oxide layer formed between the plurality of word lines.
5 . A three-dimensional flash memory having a structure for efficient layout, the three-dimensional flash memory comprising:
at least one cell block each including a plurality of memory cell strings extending on a substrate in one direction;
a plurality of peripheral circuit blocks, each including at least one peripheral circuit and located below the at least one cell block as a cell on peripheral (COP) structure is applied;
a row decoder for the at least one cell block and the plurality of peripheral circuit blocks; and
a column decoder for the at least one cell block and the plurality of peripheral circuit blocks,
wherein the row decoder and the column decoder are arranged while dividing the plurality of peripheral circuit blocks such that the plurality of peripheral circuit blocks are symmetrical to each other.
6 . The three-dimensional flash memory of claim 5 , wherein the row decoder and the column decoder are arranged in a cross shape in a plane of the three-dimensional flash memory to symmetrically divide the plurality of peripheral circuit blocks into quadrants formed by the cross shape.
7 . The three-dimensional flash memory of claim 6 , wherein the row decoder and the column decoder are arranged in the cross shape as the row decoder is located in a vertical direction and the column decoder is located in a horizontal direction across a midpoint of the row decoder in the plane of the 3D flash memory.
8 . The three-dimensional flash memory of claim 5 , wherein the row decoder and the column decoder are arranged in a T-shape in a plane of the three-dimensional flash memory and symmetrically divide the plurality of peripheral circuit blocks into two quadrants formed by the T-shape.
9 . The three-dimensional flash memory of claim 8 , wherein the row decoder and the column decoder are arranged in the T-shape as the column decoder is located in a horizontal direction and the row decoder is located in a vertical direction from a midpoint of the column decoder to one point in the plane of the three-dimensional flash memory.