IP Library › Granted Patent US 12,628,368
Granted Patent B2
US 12,628,368 · App. 17/281,820 · Granted May 12, 2026

Semiconductor device and method of manufacturing semiconductor device

Inventors: Ryohei Nonoda (Tokyo, JP); Atsushi Era (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H10D30/475H10D62/8503
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Quick Facts
Patent No.
US 12,628,368
App. No.
17/281,820
Granted
May 12, 2026
Kind
B2
Abstract

A semiconductor device according to the present invention includes a substrate, a plurality of semiconductor layers to be overlaid on the substrate and a gate electrode, a drain electrode, and a source electrode provided on the plurality of semiconductor layers, wherein each of the plurality of semiconductor layers includes a channel layer made with GaN and a barrier layer provided in contact with an upper surface of the channel layer and made with Al x Ga 1-x N, and a carbon concentration of the channel layer included in an uppermost semiconductor layer among the plurality of semiconductor layers is lower than an average value of carbon concentration of the channel layer included in the at least one semiconductor layer other than the uppermost semiconductor layer among the plurality of semiconductor layers.

Claims (16)

1 . A semiconductor device comprising:

a substrate;

a plurality of pairs of semiconductor layers on the substrate; and

a gate electrode, a drain electrode, and a source electrode provided on the plurality of pairs of semiconductor layers, wherein

each of the plurality of pairs of semiconductor layers includes a channel layer made with GaN and a barrier layer provided in contact with an upper surface of the channel layer and made with Al x Ga 1-xN ,

a carbon concentration of the channel layer included in an uppermost pair of semiconductor layers among the plurality of pairs of semiconductor layers is lower than an average value of carbon concentration of the channel layers included in the pairs of semiconductor layers other than the uppermost pair of semiconductor layers, and

the uppermost pair of semiconductor layers is an uppermost pair of channel and barrier layers in the semiconductor device.

2 . The semiconductor device according to claim 1 , wherein a two-dimensional electron gas is formed at an interface with the barrier layer in the channel layer in each of the plurality of pairs of semiconductor layers.

3 . The semiconductor device according to claim 1 , wherein the channel layer included in the uppermost pair of semiconductor layers is thinner than the channel layer included in one of the pairs of semiconductor layers other than the uppermost pair of semiconductor layers.

4 . The semiconductor device according to claim 1 , wherein the carbon concentration of the channel layer included in the uppermost pair of semiconductor layers is lower than the carbon concentration of the channel layer included in the pair of semiconductor layers immediately below the uppermost pair of semiconductor layers.

5 . The semiconductor device according to claim 1 , wherein the channel layer included in the uppermost pair of semiconductor layers and the barrier layer included in the pair of semiconductor layers immediately below the uppermost pair of semiconductor layers contact each other.

6 . The semiconductor device according to claim 1 , wherein a sum of respective film thicknesses of the channel layer included in the uppermost pair of semiconductor layers and the barrier layer included in the pair of semiconductor layers immediately below the uppermost pair of semiconductor layers is 20 nm or less.

7 . The semiconductor device according to claim 1 , wherein in each barrier layer included in each of the pairs of semiconductor layers other than the uppermost pair of semiconductor layers-layer, x is 0.2 or more.

8 . The semiconductor device according to claim 1 , wherein the carbon concentration of the channel layer included in the uppermost pair of semiconductor layers is 3×10 16 cm −3 or less.

9 . The semiconductor device according to claim 1 , wherein the average value of the carbon concentration of the channel layer included in each of the pairs of semiconductor layers other than the uppermost pair of semiconductor layers is 1×10 16 cm −3 or more.

10 . The semiconductor device according to claim 1 , wherein the channel layer included in an uppermost pair of semiconductor layers among the plurality of pairs of semiconductor layers includes carbon as an impurity.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2021
From: NONODA, RYOHEI; ERA, ATSUSHI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 055786/0162 →
Continuity (1)
Related Publication 20220020870A1 · Jan 20, 2022
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