Memory device and manufacturing method of the memory device
There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a stack structure including gate lines stacked to be spaced apart from each other; main plugs arranged to be spaced apart from each other; plug isolation patterns isolating the main plugs into first and second sub-plugs; and a select isolation pattern isolating at least one gate line located between the plug isolation patterns adjacent to each other.
1 . A memory device comprising:
a stack structure including a plurality of gate lines stacked in a vertical direction over a source line, the plurality of gate lines spaced apart from each other in the vertical direction;
main plugs arranged to be spaced apart from each other in a direction parallel to the plurality of gate lines;
plug isolation patterns isolating the main plugs into first and second sub-plugs; and
a select isolation structure comprising a select isolation pattern together with the plug isolation pattern,
wherein the plurality of gate lines include at least one cell gate line and at least on select line,
wherein the select isolation pattern penetrates at least one select line, to divide the at least one select line into a first select line and a second select line formed in the same level, and
wherein the select isolation structure extends in a direction vertical to a direction in which the first sub-plug and the second sub-plug are arranged.
2 . The memory device of claim 1 , wherein the plug isolation patterns disposed between the first sub-plug and the second sub-plug.
3 . The memory device of claim 2 , wherein each of the first and second sub-plugs includes a core pillar, a channel layer, a tunnel insulating layer, a charge trap layer, and a blocking layer, which are formed in the vertical direction.
4 . The memory device of claim 1 , wherein the plug isolation patterns are formed of an insulating material.
5 . The memory device of claim 1 , wherein the plug isolation patterns penetrate the main plugs and the stack structure.
6 . The memory device of claim 1 , wherein the select isolation pattern along with the plug isolation patterns adjacent to each other isolates the at least one select line, from the plurality of gate lines, into a first drain select line and a second drain select line formed in the same level.
7 . The memory device of claim 1 , wherein the select isolation pattern penetrates at least a portion of the plug isolation patterns adjacent to each other.
8 . The memory device of claim 1 , wherein the select isolation pattern is formed in one of a circular or an elliptical shape partially overlapping with the plug isolation patterns adjacent to each other.
9 . The memory device of claim 1 , wherein the select isolation pattern is formed of an insulating material.
10 . The memory device of claim 1 , wherein the stack structure is isolated by the select isolation pattern and the plug isolation patterns.
11 . The memory device of claim 1 , wherein the select isolation pattern contacts with the plug isolation patterns adjacent to each other.
12 . The memory device of claim 1 , wherein the gate lines include source select lines, word lines and drain select lines which are stacked to be spaced apart from each other, and
wherein the drain select lines are isolated by the select isolation pattern and the plug isolation patterns into the first and second drain select lines.
13 . The memory device of claim 1 , wherein the select isolation structure isolates the plurality of gate lines by cooperation between the select isolation pattern and the plug isolation patterns.
14 . The memory device of claim 1 , wherein each of the plug isolation patterns fully penetrates the main plugs in the vertical direction.