IP Library Granted Patent US 12,631,823
Granted Patent B2
US 12,631,823 · App. 18/151,044 · Granted May 19, 2026

Packages with photonic engines and method of forming the same

Inventors: Hsing-Kuo Hsia (Jhubei, TW); Chen-Hua Yu (Hsinchu, TW); Jui Lin Chao (New Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
G02B6/132G02B6/12004G02B6/136H01L21/76898H01L23/481H01L25/167G02B2006/12104
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Quick Facts
Patent No.
US 12,631,823
App. No.
18/151,044
Granted
May 19, 2026
Kind
B2
Abstract

A method includes patterning a top silicon layer in a substrate to form a plurality of photonic devices. The substrate includes the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer. The method further includes forming a second dielectric layer to embed the plurality of photonic devices therein, forming an interconnect structure over and signally coupling to the plurality of photonic devices, bonding an electronic die to the interconnect structure, thinning the semiconductor layer, and patterning the semiconductor layer that has been thinned to form openings. The openings are filled with a dielectric material to form dielectric regions. Through-vias are formed to penetrate through the dielectric regions to electrically couple to the interconnect structure.

Claims (57)

1 . A method comprising:

patterning a top silicon layer in a substrate to form a plurality of photonic devices, wherein the substrate comprises the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer;

forming a second dielectric layer to embed the plurality of photonic devices therein;

forming an interconnect structure over and signally coupled to the plurality of photonic devices;

bonding an electronic die to the interconnect structure;

thinning the semiconductor layer;

patterning the semiconductor layer that has been thinned to form openings;

filling the openings with a dielectric material to form dielectric regions; and

forming through-vias penetrating through the dielectric regions to electrically couple to the interconnect structure.

2 . The method of claim 1 further comprising, after the semiconductor layer is thinned, forming waveguides optically coupled to the photonic devices, wherein the waveguides are formed on an opposite side of the semiconductor layer than the photonic devices.

3 . The method of claim 1 further comprising forming a reflector in one of the openings in the semiconductor layer.

4 . The method of claim 3 , wherein the reflector contacts the first dielectric layer.

5 . The method of claim 1 further comprising bonding a supporting substrate over the electronic die.

6 . The method of claim 5 , wherein the supporting substrate comprises an optical lens.

7 . The method of claim 1 further comprising:

forming a third dielectric layer, wherein the third dielectric layer is on an opposite side of the semiconductor layer than the photonic devices; and

forming a reflector extending into the third dielectric layer.

8 . The method of claim 7 , wherein the forming the reflector comprises:

etching the third dielectric layer to form a recess in the third dielectric layer; and

depositing a metal layer into the recess.

9 . The method of claim 7 , wherein the forming the reflector comprises:

etching the third dielectric layer to form a recess in the third dielectric layer; and

placing a pre-formed reflector block in the recess, wherein the pre-formed reflector block comprises a slant metal layer, and a transparent material embedding the slant metal layer therein.

10 . The method of claim 7 , wherein the forming the reflector comprises:

etching the third dielectric layer to form a recess in the third dielectric layer; and

forming optical crystals in the third dielectric layer, wherein the optical crystals have a periodic pattern.

11 . The method of claim 7 , wherein the forming the reflector comprises:

etching the third dielectric layer to form a recess in the third dielectric layer; and

placing a transparent ball in the recess.

12 . A method comprising:

patterning a top silicon layer in a substrate to form a plurality of photonic devices, wherein the substrate comprises the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer;

forming a second dielectric layer to embed the plurality of photonic devices therein;

forming an interconnect structure over and signally coupled to the plurality of photonic devices;

bonding an electronic die to the interconnect structure;

thinning the semiconductor layer;

patterning the semiconductor layer that has been thinned to form openings;

forming a reflector in one of the openings in the semiconductor layer, wherein the reflector is configured to reflect an optical signal received by the reflector to an edge coupler adjacent to the reflector;

filling the openings with a dielectric material to form dielectric regions; and

forming through-vias penetrating through the dielectric regions to electrically couple to the interconnect structure.

13 . The method of claim 12 further comprising, after the semiconductor layer is thinned, forming waveguides optically coupled to the photonic devices, wherein the waveguides are formed on an opposite side of the semiconductor layer than the photonic devices.

14 . The method of claim 12 , wherein the reflector contacts the first dielectric layer.

15 . The method of claim 12 further comprising bonding a supporting substrate over the electronic die.

16 . A method comprising:

patterning a top silicon layer in a substrate to form a plurality of photonic devices, wherein the substrate comprises the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer;

forming a second dielectric layer to embed the plurality of photonic devices therein;

forming an interconnect structure over and signally coupled to the plurality of photonic devices;

bonding an electronic die to the interconnect structure;

thinning the semiconductor layer;

patterning the semiconductor layer that has been thinned to form openings;

filling the openings with a dielectric material to form dielectric regions; and

forming through-vias penetrating through the dielectric regions to electrically couple to the interconnect structure, wherein at a time after the through-vias are formed, a portion of the semiconductor layer remains.

17 . The method of claim 16 further comprising, after the semiconductor layer is thinned, forming waveguides optically coupled to the photonic devices, wherein the waveguides are formed on an opposite side of the semiconductor layer than the photonic devices.

18 . The method of claim 16 further comprising forming a reflector in one of the openings in the semiconductor layer.

19 . The method of claim 16 further comprising bonding a supporting substrate over the electronic die, and wherein the supporting substrate comprises an optical lens.

20 . The method of claim 16 further comprising:

forming a third dielectric layer, wherein the third dielectric layer is on an opposite side of the semiconductor layer than the photonic devices; and

forming a reflector extending into the third dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2023
From: HSIA, HSING-KUO; YU, CHEN-HUA; CHAO, JUI LIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 062661/0880 →
Continuity (3)
Provisional Application 63377133 · Sep 26, 2022
Provisional Application 63376456 · Sep 21, 2022
Related Publication 20240094469A1 · Mar 21, 2024
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