Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode
The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.
1 . A circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column;
a word line drive circuit for each row having an output connected to drive the word line of the row;
a row decoder circuit coupled to the word line drive circuits;
a control circuit configured to support two modes of memory circuit operation including: a first mode where the row decoder circuit actuates only one word line in the memory array during a memory access operation and a second mode where the row decoder circuit simultaneously actuates only one word line per sub-array during an in-memory computation operation;
an input/output circuit for each column comprising:
a plurality of bit line inputs coupled to the local bit lines of the sub-arrays;
a column data output coupled to the plurality of bit line inputs and configured to generate a column data bit for output in the first mode; and
a plurality of sub-array data outputs, where each sub-array data output is coupled to a corresponding one of the plurality of bit line inputs, and configured to generate a plurality of sub-array data bits for output in the second mode; and
a processing circuit configured to receive feature data and perform a computational operation as a function of the feature data and the plurality of sub-array data bits.
2 . The circuit of claim 1 , wherein each memory cell is a static random access memory (SRAM) cell.
3 . The circuit of claim 2 , wherein the SRAM cell is an 8T-type cell, wherein the word line is a read word line of the 8T-type cell and the local bit line is a read bit line of the 8T-type cell.
4 . The circuit of claim 2 , wherein the SRAM cell is a 6T-type cell, wherein the word line is a word line of the 6T-type cell and the local bit line is one bit line of a complementary pair of bit lines for the 6T-type cell.
5 . The circuit of claim 1 , wherein each memory cell is a non-volatile memory cell with a deterministic output.
6 . The circuit of claim 1 , wherein the input/output circuit for each column further comprises, between each bit line input and a corresponding sub-array data output:
a first latch circuit and a first buffer circuit; and
a first multiplexing circuit having a first input coupled to the bit line input, an output coupled to the first latch circuit and the first buffer circuit, and a second input coupled to the output of the first multiplexing circuit;
wherein a selection input of the first multiplexing circuit is configured to receive a mode control signal, the first multiplexing circuit selecting the second input when the mode control signal is in a first state corresponding to the first mode and selecting the first input when the mode control signal is in a second state corresponding to the second mode.
7 . The circuit of claim 6 , wherein the input/output circuit for each column further comprises a read circuit coupled between the bit line input and the first input of the first multiplexing circuit.
8 . The circuit of claim 6 , wherein the input/output circuit for each column further comprises, between the plurality of bit line inputs and the column data output:
a second latch circuit and a second buffer circuit; and
a second multiplexing circuit having a first input coupled the plurality of bit line inputs, an output coupled to the second latch circuit and the second buffer circuit, and a second input coupled to the output of the second multiplexing circuit;
wherein a selection input of the second multiplexing circuit is configured to receive the mode control signal, the second multiplexing circuit selecting the first input when the mode control signal is in the first state corresponding to the first mode and selecting the second input when the mode control signal is in the second state corresponding to the second mode.
9 . The circuit of claim 8 , wherein the input/output circuit for each column further comprises a read circuit coupled between the plurality of bit line inputs and the first input of the second multiplexing circuit.
10 . The circuit of claim 1 , wherein the input/output circuit for each column further comprises, between a column data input and a column write bit line coupled to the memory array:
a write logic circuit; and
a third multiplexing circuit having a first input coupled to the column data input and a second input coupled by a logic inverter to the column data input;
wherein a selection input of the third multiplexing circuit is configured to receive an invert control signal, the third multiplexing circuit selecting the first input when the invert control signal is in a first state for writing non-inverted data to the memory array and selecting the second input when the invert control signal is in a second state for writing inverted data to the memory array.
11 . The circuit of claim 10 , wherein the input/output circuit for each column further comprises, between each bit line input and a corresponding sub-array data output:
a fourth multiplexing circuit having a first input coupled to the bit line input and a second input coupled by a logic inverter to the bit line input;
wherein a selection input of the fourth multiplexing circuit is configured to receive the invert control signal, the fourth multiplexing circuit selecting the first input when the invert control signal is in the first state for reading non-inverted data from the memory array and selecting the second input when the invert control signal is in the second state for reading inverted data from the memory array.
12 . The circuit of claim 11 , wherein the input/output circuit for each column further comprises, between each bit line input and the corresponding sub-array data output:
a first latch circuit and a first buffer circuit; and
a first multiplexing circuit having a first input coupled to an output of the fourth multiplexing circuit, an output coupled to the first latch circuit and the first buffer circuit, and a second input coupled to the output of the first multiplexing circuit;
wherein a selection input of the first multiplexing circuit is configured to receive a mode control signal, the first multiplexing circuit selecting the second input when the mode control signal is in a first state corresponding to the first mode and selecting the first input when the mode control signal is in a second state corresponding to the second mode.
13 . The circuit of claim 11 , wherein the invert control signal is associated with a specific sub-array of the plurality of sub-arrays.
14 . The circuit of claim 1 :
wherein the row decoder circuit comprises a plurality of sub-decoder circuits corresponding to the plurality of sub-arrays;
wherein the control circuit is configured to receive an address and includes a predecoder circuit configured to predecode the address and generate decoder control signals for application to the plurality of sub-decoder circuits; and
wherein each sub-decoder circuit selectively generates a word line signal on a word line in response to said decoder control signals.
15 . The circuit of claim 14 , wherein in the first mode only one of the plurality of sub-decoder circuits generates one word line signal and wherein in the second mode each of the plurality of sub-decoder circuits generates one word line signal on a word line.
16 . The circuit of claim 15 , wherein the control circuit is configured to generate a mask signal, and wherein each of the plurality of sub-decoder circuits is selectively enabled for generating the one word line signal in response to the mask signal.
17 . The circuit of claim 1 :
wherein the row decoder circuit comprises a plurality of sub-decoder circuits corresponding to the plurality of sub-arrays;
wherein the control circuit is configured, in the first mode, to receive a first address and includes a first predecoder circuit configured to predecode the first address and generate decoder control signals for application to the plurality of sub-decoder circuits; and
wherein only one of the plurality of sub-decoder circuits generates one word line signal on a word line in response to said decoder control signals.
18 . The circuit of claim 1 :
wherein the row decoder circuit comprises a plurality of sub-decoder circuits corresponding to the plurality of sub-arrays;
wherein the control circuit is configured, in the second mode, to receive a plurality of second addresses corresponding to the plurality of sub-decoder circuits and includes a second predecoder circuit configured to predecode the plurality of second addresses and generate decoder control signals for application to the plurality of sub-decoder circuits; and
wherein each of the plurality of sub-decoder circuits generates one word line signal on a selected word line in response to said decoder control signals.
19 . A circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column;
a word line drive circuit for each row having an output connected to drive the word line of the row;
a row decoder circuit coupled to the word line drive circuits, where the row decoder circuit operates in a first mode for memory read access to actuate only one word line in the memory array, and wherein the row decoder operates in a second mode during an in-memory computation operation to simultaneously actuate only one word line per sub-array;
an input/output circuit for each column comprising:
a plurality of bit line inputs coupled to the local bit lines of the sub-arrays;
a column data output coupled to the plurality of bit line inputs and configured to generate a column data bit for output in the first mode for memory read access; and
a plurality of sub-array data outputs, where each sub-array data output is coupled to a corresponding one of the plurality of bit line inputs, and configured to generate a plurality of sub-array data bits for output in the second mode for in-memory computation operation.
20 . The circuit of claim 19 , wherein the input/output circuit for each column further comprises, between each bit line input and corresponding sub-array data output:
a first latch circuit and a first buffer circuit; and
a first multiplexing circuit having a first input coupled to the bit line input, an output coupled to the first latch circuit and the first buffer circuit, and a second input coupled to the output of the first multiplexing circuit;
wherein a selection input of the first multiplexing circuit is configured to receive a mode control signal, the first multiplexing circuit selecting the second input when the mode control signal is in a first state and selecting the first input when the mode control signal is in a second state.
21 . The circuit of claim 20 , wherein the input/output circuit for each column further comprises a read circuit coupled between the bit line input and the first input of the first multiplexing circuit.
22 . The circuit of claim 20 , wherein the input/output circuit for each column further comprises, between the plurality of bit line inputs and the column data output:
a second latch circuit and a second buffer circuit; and
a second multiplexing circuit having a first input coupled the plurality of bit line inputs, an output coupled to the second latch circuit and the second buffer circuit, and a second input coupled to the output of the second multiplexing circuit;
wherein a selection input of the second multiplexing circuit is configured to receive the mode control signal, the second multiplexing circuit selecting the first input when the mode control signal is in the first state and selecting the second input when the mode control signal is in the second state.
23 . The circuit of claim 22 , wherein the input/output circuit for each column further comprises a read circuit coupled between the plurality of bit line inputs and the first input of the second multiplexing circuit.