Data processing system, buffer circuit and method for operating buffer circuit
A buffer circuit including a memory circuit and a control circuit is provided. The memory circuit stores an input data from a data transmitting device, and transmits an output data to a data receiving device. The control circuit computes a remaining data volume of the memory circuit, and generates a control signal according to the remaining data volume. The remaining data volume represents a volume of data to be transmitted which are stored in the memory circuit. The control signal controls the data transmitting device to generate a write clock signal, and the control circuit reduces a frequency of the write clock signal by the control signal when the remaining data volume increases.
1 . A buffer circuit, comprising:
a memory circuit, configured to store an input data from a data transmitting device, configured to transmit an output data to a data receiving device, and configured to receive a read-enable signal from the data receiving device; and
a control circuit, configured to compute a remaining data volume of the memory circuit, and configured to generate a control signal having periodical pulses according to the remaining data volume, wherein the remaining data volume is indicative of a volume of data to be transmitted which are stored in the memory circuit,
wherein the control signal is configured to control the data transmitting device to generate a write clock signal;
wherein in response to the read-enable signal having a first logic level, the control circuit is configured to periodically disable a clock generating circuit of the data transmitting device by the control signal from generating the write clock signal so as to gradually reduce a frequency of the write clock signal when the remaining data volume increases from a first threshold value to a second threshold value, thereby gradually adjusting the frequency of the write clock signal from a first frequency to a second frequency.
2 . The buffer circuit of claim 1 , wherein the control signal is configured to disable the data transmitting device from generating the write clock signal, and the control circuit increases a duty cycle of the control signal when the remaining data volume increases.
3 . The buffer circuit of claim 1 , wherein the memory circuit conducts a write operation to store the input data according to the write clock signal of the data transmitting device.
4 . The buffer circuit of claim 1 , wherein the control signal is configured to disable the data transmitting device from generating the write clock signal, and the control circuit is configured to compare the remaining data volume with a plurality of different third threshold values, wherein the control circuit increases a pulse width of the control signal when the remaining data volume increases to reach one of the plurality of third threshold values, wherein the control circuit sets a duty cycle of the control signal to 100% when the remaining data volume increases to reach a maximum one of the plurality of third threshold values.
5 . The buffer circuit of claim 1 , wherein the data transmitting device and the data receiving device belong to different clock domains.
6 . The buffer circuit of claim 1 , wherein the data transmitting device and the data receiving device belong to a same clock domain, and the data transmitting device and the data receiving device conduct an asynchronous data transmission.
7 . The buffer circuit of claim 1 , wherein the memory circuit has a write pointer and a read pointer, and the control circuit subtracts the read pointer from the write pointer to obtain the remaining data volume.
8 . The buffer circuit of claim 1 , wherein the memory circuit is a first-in-first-out (FIFO) memory circuit.
9 . A method for operating a buffer circuit, comprising:
storing an input data of a data transmitting device in a memory circuit so as to transmit an output data to a data receiving device from the memory circuit;
receiving a read-enable signal from the data receiving device;
computing a remaining data volume of the memory circuit, wherein the remaining data volume is indicative of a volume of data to be transmitted which are stored in the memory circuit; and
generating a control signal having periodical pulses according to the remaining data volume, comprising:
when the control signal is configured to control the data transmitting device to generate a write clock signal, in response to the read-enable signal having a first logic level, periodically disabling a clock generating circuit of the data transmitting device by the control signal from generating the write clock signal so as to gradually reduce a frequency of the write clock signal when the remaining data volume increases from a first threshold value to a second threshold value, thereby gradually adjusting the frequency of the write clock signal from a first frequency to a second frequency; and
when the control signal is configured to control the data receiving device to generate a read clock signal, in response to the read-enable signal having a second logic level, periodically disabling a clock generating circuit of the data receiving device by the control signal from generating the read clock signal so as to gradually reduce a frequency of the read clock signal when the remaining data volume decreases from a third threshold value to a forth threshold value, thereby gradually adjusting the frequency of the read clock signal from a third frequency to a forth frequency.
10 . The method of claim 9 , wherein generating the control signal according to the remaining data volume comprises:
adjusting a duty cycle of the control signal according to the remaining data volume;
when the control signal is configured to disable the data transmitting device from generating the write clock signal, increasing the duty cycle of the control signal when the remaining data volume increases; and
when the control signal is configured to disable the data receiving device from generating the read clock signal, increasing the duty cycle of the control signal when the remaining data volume decreases.
11 . The method of claim 9 , wherein the memory circuit conducts a write operation to store the input data according to the write clock signal of the data transmitting device, and the memory circuit conducts a read operation to transmit the output data to the data receiving device according to the read clock signal of the data receiving device.
12 . The method of claim 9 , wherein the control signal is configured to disable the write clock signal, wherein reducing the frequency of the write clock signal by the control signal when the remaining data volume increases comprises:
comparing the remaining data volume with a plurality of different fifth threshold values; and
when the remaining data volume increases to reach one of the plurality of fifth threshold values, increasing a pulse width of the control signal, wherein when the remaining data volume increases to reach a maximum one of the plurality of fifth threshold values, a duty cycle of the control signal is set to 100%,
wherein reducing the frequency of the read clock signal by the control signal when the remaining data volume decreases comprises:
comparing the remaining data volume with a plurality of different sixth threshold values; and
when the remaining data volume decreases to reach one of the plurality of sixth threshold values, increasing the pulse width of the control signal, wherein when the remaining data volume decreases to reach a minimum one of the plurality of sixth threshold values, the duty cycle of the control signal is set to 100%.
13 . The method of claim 9 , wherein the data transmitting device and the data receiving device belong to different clock domains.
14 . The method of claim 9 , wherein the data transmitting device and the data receiving device belong to a same clock domain, and the data transmitting device and the data receiving device conduct an asynchronous data transmission.
15 . The method of claim 9 , wherein computing the remaining data volume of the memory circuit comprises:
receiving a write pointer and a read pointer of the memory circuit; and
subtracting the read pointer from the write pointer to obtain the remaining data volume.
16 . The method of claim 9 , wherein the memory circuit is a first-in-first-out (FIFO) memory circuit.
17 . A buffer circuit, comprising:
a memory circuit, configured to store an input data from a data transmitting device, configured to transmit an output data to a data receiving device, and configured to receive a read-enable signal from the data receiving device; and
a control circuit, configured to compute a remaining data volume of the memory circuit, and configured to generate a control signal having periodical pulses according to the remaining data volume, wherein the remaining data volume is indicative of a volume of data to be transmitted which are stored in the memory circuit,
wherein the control signal is configured to control the data receiving device to generate a read clock signal, in response to the read-enable signal having a second logic level, the control circuit periodically disables a clock generating circuit of the data receiving device by the control signal from generating the read clock signal so as to gradually reduce a frequency of the read clock signal when the remaining data volume decreases from a first threshold value to a second threshold value, thereby gradually adjusting the frequency of the read clock signal from a third frequency to a forth frequency.
18 . The buffer circuit of claim 17 , wherein the control signal is configured to disable the data receiving device from generating the read clock signal, and the control circuit increases a duty cycle of the control signal when the remaining data volume decreases.
19 . The buffer circuit of claim 17 , wherein the memory circuit conducts a read operation to transmit the output data to the data receiving device according to the read clock signal of the data receiving device.
20 . The buffer circuit of claim 17 , wherein the control signal is configured to disable the data receiving device from generating the read clock signal, and the control circuit is configured to compare the remaining data volume with a plurality of different third threshold values, wherein the control circuit increases a pulse width of the control signal when the remaining data volume decrease to reach one of the plurality of third threshold values, wherein the control circuit sets a duty cycle of the control signal to 100% when the remaining data volume decreases to reach a minimum one of the plurality of third threshold values.