SRAM cells for low temperature integrated circuit operation
Integrated circuits including static random-access memory (SRAM) bit-cells that are actively cooled to a low temperature (e.g., in the cryogenic range) where transistor drive currents become significantly increased and transistor leakage currents significantly reduced. With the drive current improvement, bit-cell capacitance may be reduced by defining narrower transistor fin structures and/or four transistor (4T) bit-cells may be implemented, for example with two parallel transistor fins and colinear gate electrodes.
1 . A computer system, comprising:
an integrated circuit (IC) die, comprising:
arithmetic logic unit (ALU) circuitry comprising a plurality of first transistors, each of the first transistors comprising a stack of first channel regions of first fins having a first width of at least 3 nm; and
a static random-access memory (SRAM), wherein:
a bit-cell of the SRAM consists of four NMOS transistors;
the NMOS transistors are second transistors, each of the second transistors comprising a stack of second channel regions of second fins having a second width no more than 2 nm;
the bit-cell has no more than two second fins;
individual ones of the second fins comprise the stack of second channel regions for one access transistor and for one pull-down transistor; and
the second fins have a fin spacing: fin width ratio that is 2-3 times the fin spacing: fin width ratio of the first fins; and
an integrated cooling structure comprising a plurality of microchannels within the IC die, the microchannels to convey a heat transfer liquid that maintains at least the SRAM at a temperature below −50° C. during steady state operation of the SRAM.
2 . The system of claim 1 , wherein:
the second fins have first longitudinal lengths in a first direction;
the four NMOS transistors comprise gate electrodes having second longitudinal lengths in a second direction, orthogonal to the first direction;
a centerline passing through a thickness of the gate electrode of a first access transistor is substantially colinear with a centerline passing through a thickness of the gate electrode of a first pull-down transistor; and
a centerline passing through a thickness of the gate electrode of a second access transistor is substantially colinear with a centerline passing through a thickness of the gate electrode of a second pull-down transistor.
3 . The system of claim 2 , wherein:
the four NMOS transistors comprise source/drain contact metallization having third longitudinal lengths in the second direction;
a first source/drain contact metallization of the first pull-down transistor and a first source/drain contact metallization of the second pull-down transistor comprise a single contiguous stripe of metallization spanning the second fins and a space therebetween;
a centerline passing through a thickness of a second source/drain contact metallization of the first pull-down transistor is substantially colinear with a centerline passing through a thickness of a second source/drain contact metallization of the first access transistor; and
a centerline passing through a thickness of a second source/drain contact metallization of the second pull-down transistor is substantially colinear with a centerline passing through a thickness of a second source/drain contact metallization of the second access transistor.
4 . The system of claim 1 , further comprising a power supply coupled with the IC die to power the IC die during operation.