IP Library › Granted Patent US 12,633,874
Granted Patent B2
US 12,633,874 · App. 18/938,191 · Granted May 19, 2026

Switchable active element for inductor-capacitor (LC) voltage controlled oscillator

Inventors: Burcin Serter Ergun (Poway, CA); Jose Luis Sanchez (Chula Vista, CA); Sajin Mohamad (San Diego, CA); Zhiqin Chen (San Diego, CA); Ashwith Jerome Rego (Bangalore, IN)
Assignee: QUALCOMM Incorporated
H03B5/04H03B5/1212H03B2200/0088
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Quick Facts
Patent No.
US 12,633,874
App. No.
18/938,191
Granted
May 19, 2026
Kind
B2
Abstract

An apparatus, comprising: a first upper voltage rail; a lower voltage rail; a set of voltage controlled oscillator (VCO) active cores, wherein one or more of the set of VCO active cores is selectively coupled to the first upper voltage rail based on a control signal, wherein the set of the VCO active cores are coupled to the lower voltage rail or the one or more of the set of VCO active cores is selectively coupled to the lower voltage rail based on the control signal; and a tank circuit coupled to the set of VCO active cores.

Claims (28)

1 . An apparatus, comprising:

a first upper voltage rail;

a lower voltage rail;

a set of voltage controlled oscillator (VCO) active cores, wherein one or more of the set of VCO active cores is selectively coupled to the first upper voltage rail based on a control signal, wherein the set of the VCO active cores are coupled to the lower voltage rail or the one or more of the set of VCO active cores is selectively coupled to the lower voltage rail based on the control signal;

a tank circuit coupled to the set of VCO active cores; and

a control circuit, including

a differential difference amplifier configured to generate a calibration signal based on a first difference between first and second voltages at respective ports of the tank circuit, and a second difference between first and second reference voltages; and

a calibration engine configured to generate the control signal based on the calibration signal.

2 . The apparatus of claim 1 , further comprising a control circuit configured to generate the control signal.

3 . The apparatus of claim 2 , further comprising a first set of switching devices coupled between the first upper voltage rail and the set of VCO active cores, respectively, wherein the control circuit is coupled to the first set of switching devices.

4 . The apparatus of claim 3 , wherein the first set of switching devices comprise at least one set of single pole double throw (SPDT) switching devices including enable terminals coupled to the first upper voltage rail, disable terminals coupled to ground, and pole terminals coupled to the set of VCO active cores, respectively.

5 . The apparatus of claim 2 , further comprising a second set of switching devices coupled between the set of VCO active cores and the lower voltage rail, respectively, and wherein the control circuit is coupled to the second set of switching devices.

6 . The apparatus of claim 5 , wherein the second set of switching devices comprise at least one set of single pole double throw (SPDT) switching devices including enable terminals coupled to the lower voltage rail, disable terminals coupled to ground, and pole terminals coupled to the set of VCO active cores, respectively.

7 . The apparatus of claim 1 , further comprising a low dropout (LDO) voltage regulator coupled between a second upper voltage rail and the first upper voltage rail, wherein the LDO voltage regulator is configured to receive a reference voltage for controlling a supply voltage at the first upper voltage rail.

8 . The apparatus of claim 7 , further comprising a control circuit configured to control the reference voltage.

9 . The apparatus of claim 1 , wherein the tank circuit comprises an inductor-capacitor (LC) tank circuit.

10 . The apparatus of claim 1 , wherein each of the set of VCO active cores comprises cross-coupled field effect transistors (FETs) including drains coupled to first and second ports of the tank circuit, respectively.

11 . The apparatus of claim 10 , wherein the cross-coupled FETs each comprises an n-channel field effect transistor (FET).

12 . The apparatus of claim 1 , wherein each of the set of VCO active cores comprises cross-coupled inverters including outputs coupled to first and second ports of the tank circuit, respectively.

13 . The apparatus of claim 1 , further comprising a low dropout (LDO) voltage regulator coupled between a second upper voltage rail and the first upper voltage rail, wherein the LDO voltage regulator is configured to receive a reference voltage for controlling a supply voltage at the first upper voltage rail, and wherein the calibration engine is configured to control the reference voltage based on the calibration signal.

14 . The apparatus of claim 1 , wherein the tank circuit is configured to receive a frequency control signal in accordance with an operation of a phase locked loop (PLL).

15 . A method, comprising:

operating a first set of switching devices to selectively couple one or more of a set of voltage controlled oscillator (VCO) active cores to a first upper voltage rail based on a configuration parameter, wherein the set of VCO active cores are coupled to a tank circuit; and

setting a reference voltage applied to a low dropout (LDO) voltage regulator based on the configuration parameter, the LDO voltage regulator coupled between a second upper voltage rail and the first upper voltage rail,

wherein the configuration parameter is based on a first difference between first and second voltages at respective ports of the tank circuit, and a second difference between first and second reference voltages.

16 . The method of claim 15 , wherein the configuration parameter is based on a power consumption of the set of VCO active cores.

17 . The method of claim 15 , wherein the configuration parameter is based on a noise in a supply voltage at the first upper voltage rail.

18 . The method of claim 15 , further comprising generating a clock signal at a port of the tank circuit based on a frequency control voltage applied to the tank circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2024
From: ERGUN, BURCIN SERTER; SANCHEZ, JOSE LUIS; MOHAMAD, SAJIN; CHEN, ZHIQIN; REGO, ASHWITH JEROME
To: QUALCOMM INCORPORATED
Reel/Frame 069487/0149 →
Continuity (1)
Related Publication 20260128712A1 · May 7, 2026
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