Semiconductor devices including a plurality of fins with corresponding gate oxide layers, fabrication methods thereof, 3D memories and memory devices
Examples of the present application provide a semiconductor device, a fabrication method thereof, a 3D memory and a memory device, wherein the semiconductor device includes: a substrate including first fins and second fins; a first gate oxide layer disposed on the first fins; a second gate oxide layer disposed on the second fins, wherein the sum of the thicknesses of the first fin and the first gate oxide layer is less than or equal to the sum of the thicknesses of the second fin and the second gate oxide layer; and a gate layer disposed on the first gate oxide layer and the second gate oxide layer. In the way described above, difficulty of etching process is reduced and yield and performance of products are improved.
1 . A semiconductor device, comprising:
a substrate comprising first fins and second fins;
a first isolation structure disposed between an adjacent two of the first fins;
a first gate oxide layer disposed on the first fins, wherein a sum of a thickness of a first fin of the first fins and a thickness of the first gate oxide layer is less than or equal to a thickness of the first isolation structure;
a second gate oxide layer disposed on the second fins, wherein the sum of the thickness of the first fin and the thickness of the first gate oxide layer is less than or equal to a sum of a thickness of a second fin of the second fins and a thickness of the second gate oxide layer; and
a gate layer disposed on the first gate oxide layer and the second gate oxide layer.
2 . The semiconductor device of claim 1 , wherein the thickness of the first fin is less than the thickness of the second fin.
3 . The semiconductor device of claim 1 , further comprising:
second isolation structures disposed between adjacent two of the second fins; and
a third isolation structure disposed between the first fin and the second fin adjacent to the first fin.
4 . The semiconductor device of claim 3 , wherein a thickness of a second isolation structure of the second isolation structures is less than the thickness of the second fin.
5 . The semiconductor device of claim 4 , wherein the second gate oxide layer is disposed on a side surface and a top surface of a portion of the second fin protruding above the second isolation structure and is connected with the second isolation structure.
6 . The semiconductor device of claim 3 , wherein a thickness of the third isolation structure on a side proximate to the first isolation structure is equal to a thickness of the first isolation structure, and wherein a thickness of the third isolation structure on a side proximate to a second isolation structure of the second isolation structures is equal to the thickness of the second isolation structure.
7 . The semiconductor device of claim 1 , wherein the first gate oxide layer and the second gate oxide layer are comprised of dielectric materials.
8 . The semiconductor device of claim 1 , wherein the gate layer includes gates of at least one of a field effect transistor or a planar transistor in the semiconductor device.
9 . The semiconductor device of claim 1 , further including a first well region and a second well region, wherein threshold voltages of devices in the first well region are higher than threshold voltages of devices in the second well region.
10 . The semiconductor device of claim 1 , wherein the thickness of the first fin is measured from a bottom surface of the substrate to a top surface of the first fin, and the thickness of the second fin is measured from the bottom surface of the substrate to a top surface of the second fin.
11 . A method of fabricating a semiconductor device, wherein the semiconductor device comprises a first well region and a second well region, and the method of fabricating the semiconductor device comprises:
providing a substrate;
forming the substrate having a thickness in the first well region being less than a thickness in the second well region, wherein forming the substrate further comprises:
forming a first sacrificial layer on the substrate in the first well region and the second well region;
forming a second sacrificial layer on the first sacrificial layer in the first well region and the second well region;
forming a third sacrificial layer on the second sacrificial layer in the second well region; and
thinning the first well region to remove the first sacrificial layer and the second sacrificial layer in the first well region and to make the thickness of the substrate in the first well region less than the thickness of the substrate in the second well region;
forming a first gate oxide layer on the substrate in the first well region;
processing the substrate and the first gate oxide layer to form first fins on the substrate in the first well region and form second fins on the substrate in the second well region;
forming a second gate oxide layer on the second fins, wherein a sum of a thickness of a first fin of the first fins and a thickness of the first gate oxide layer is less than or equal to a sum of a thickness of a second fin of the second fins and a thickness of the second gate oxide layer;
forming a gate layer on the first gate oxide layer and the second gate oxide layer; and
planarizing the gate layer.
12 . The method of fabricating the semiconductor device of claim 11 , wherein processing the substrate and the first gate oxide layer to form the first fins on the substrate in the first well region and form the second fins on the substrate in the second well region comprises:
removing the second sacrificial layer;
forming a fourth sacrificial layer on the first gate oxide layer in the first well region and on the first sacrificial layer in the second well region;
forming a fifth sacrificial layer on the fourth sacrificial layer in the first well region and the second well region;
forming first trenches on the substrate in the first well region, forming second trenches on the substrate in the second well region, and forming a third trench on the substrate at a boundary between the first well region and the second well region, wherein the first fins and the second fins are formed on the substrate; and
forming first isolation structures in the first trenches, forming second isolation structures in the second trenches, and forming a third isolation structure in the third trench.
13 . The method of fabricating the semiconductor device of claim 12 , wherein before forming the second gate oxide layer on the second fins, the method further comprises:
thinning the first well region and the second well region to expose the fourth sacrificial layer;
thinning the second well region to expose the first sacrificial layer; and
thinning the first well region and the second well region to expose the first gate oxide layer and make a thickness of a second isolation structure of the second isolation structures less than the thickness of the second fin.
14 . The method of fabricating the semiconductor device of claim 13 , characterized in that thinning the first well region and the second well region to expose the first gate oxide layer comprises thinning the first well region and the second well region to make the sum of the thickness of the first fin and the thickness of the first gate oxide layer less than or equal to the thickness of the second fin.
15 . A storage system, comprising:
a memory including:
a substrate comprising first fins and second fins;
a first isolation structure disposed between an adjacent two of the first fins;
a first gate oxide layer disposed on the first fins, wherein a sum of a thickness of a first fin of the first fins and a thickness of the first gate oxide layer is less than or equal to a thickness of the first isolation structure;
a second gate oxide layer disposed on the second fins, wherein the sum of the thickness of the first fin and the thickness of the first gate oxide layer is less than or equal to a sum of a thickness of a second fin of the second fins and a thickness of the second gate oxide layer; and
a gate layer disposed on the first gate oxide layer and the second gate oxide layer; and
a controller coupled to the memory.
16 . The storage system of claim 15 , wherein the thickness of the first fin is less than the thickness of the second fin.
17 . The storage system of claim 15 , further comprising:
second isolation structures disposed between adjacent two of the second fins; and
a third isolation structure disposed between the first fin and the second fin adjacent to the first fin.
18 . The storage system of claim 17 , wherein a thickness of a second isolation structure of the second isolation structures is less than the thickness of the second fin.
19 . The storage system of claim 18 , wherein the second gate oxide layer is disposed on a side surface and a top surface of a portion of the second fin protruding above the second isolation structure and is connected with the second isolation structure.
20 . The storage system of claim 17 , wherein a thickness of the third isolation structure on a side proximate to the first isolation structure is equal to a thickness of the first isolation structure, and wherein a thickness of the third isolation structure on a side proximate to a second isolation structure of the second isolation structures is equal to the thickness of the second isolation structure.