Semiconductor structure including different devices and methods for manufacturing the same

1 . A method for manufacturing a semiconductor structure, comprising:

forming a first fin portion and a second fin portion on a semiconductor substrate, the first fin portion and the second fin portion being displaced from each other;

forming a first stack on the first fin portion, the first stack including

at least one lower channel portion,

at least one upper channel portion, and

a middle channel portion which is formed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion;

forming a second stack on the second fin portion, the second stack including

at least one lower channel portion,

at least one upper channel portion, and

a middle isolation portion which is formed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion;

forming two first source/drain portions on the first fin portion, the two first source/drain portions being spaced apart from each other such that each of the at least one lower channel portion, the at least one upper channel portion and the middle channel portion in the first stack extends between the two first source/drain portions;

forming two lower source/drain portions on the second fin portion, the two lower source/drain portions being spaced apart from each other such that the at least one lower channel portion in the second stack extends between the two lower source/drain portions; and

forming two upper source/drain portions which are respectively above and spaced apart from the two lower source/drain portions such that the at least one upper channel portion in the second stack extends between the two upper source/drain portions,

a first sum of a number of the at least one lower channel portion, a number of the at least one upper channel portion and a number of the middle channel portion in the first stack being greater than a number of the at least one lower channel portion in the second stack and greater than a number of the at least one upper channel portion in the second stack.

2 . The method as claimed in claim 1 , wherein formation of the first stack and the second stack includes:

forming a first stack unit and a second stack unit respectively on the first fin portion and the second fin portion, each of the first stack unit and the second stack unit including

a first set of portions which include the at least one lower channel portion, the at least one upper channel portion and a preformed portion that is disposed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion, and

a second set of portions which include at least three sacrificial portions, and which are disposed to alternate with the first set of portions;

replacing the preformed portion in the first stack unit with the middle channel portion;

removing the at least three sacrificial portions in the first stack unit, thereby obtaining the first stack on the first fin portion;

replacing the preformed portion in the second stack unit with the middle isolation portion; and

removing the at least three sacrificial portions in the second stack unit, thereby obtaining the second stack on the second fin portion.

3 . The method as claimed in claim 2 , wherein formation of the first stack unit and the second stack unit includes:

forming a laminated structure on a starting substrate, the laminated structure including

a first set of layers which include at least one lower channel layer, at least one upper channel layer and a preformed layer that is disposed between and spaced apart from the at least one lower channel layer and the at least one upper channel layer, and

a second set of layers which include at least three sacrificial layers, and which are disposed to alternate with the first set of layers; and

performing a patterning process such that

the starting substrate is patterned into the semiconductor substrate, the first fin portion and the second fin portion,

the at least one lower channel layer, the at least one upper channel layer and the preformed layer are respectively patterned into the at least one lower channel portion, the at least one upper channel portion and the preformed portion in each of the first stack unit and the second stack unit, and

the at least three sacrificial layers are respectively patterned into the at least three sacrificial portions in each of the first stack unit and the second stack unit.

4 . A method for manufacturing a semiconductor structure, comprising:

forming a first fin portion and a second fin portion on a semiconductor substrate, the first fin portion and the second fin portion being displaced from each other;

forming a first stack on the first fin portion, the first stack including first channel portions spaced apart from each other;

forming a second stack on the second fin portion, the second stack including at least one lower channel portion, at least one upper channel portion and a middle isolation portion which is formed between and spaced apart from the at least one lower channel portion and the at least one upper channel portion;

forming two first source/drain portions on the first fin portion, the two first source/drain portions being spaced apart from each other such that each of the first channel portions extends between the two first source/drain portions;

forming two lower source/drain portions on the second fin portion, the two lower source/drain portions being spaced apart from each other such that the at least one lower channel portion extends between the two lower source/drain portions;

forming two upper source/drain portions which are respectively above and spaced apart from the two lower source/drain portions such that the at least one upper channel portion extends between the two upper source/drain portions; and

forming two isolation structures each of which is formed between one of the two lower source/drain portions and a corresponding one of the two upper source/drain portions,

a number of the first channel portions being greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.

5 . The method as claimed in claim 4 , wherein formation of the first stack and the second stack includes:

forming a first laminated structure on a first region of a starting substrate, the first laminated structure including first channel layers and first sacrificial layers formed to alternate with the first channel layers;

forming a second laminated structure on a second region of the starting substrate, the second laminated structure including

a first set of layers which include at least one lower channel layer, at least one upper channel layer and a preformed layer that is disposed between and spaced apart from the at least one lower channel layer and the at least one upper channel layer, and

a second set of layers which include at least three second sacrificial layers and which are disposed to alternate with the first set of layers;

performing a patterning process to form two first source/drain recesses in the first lamination structure and two second source/drain recesses in the second lamination structure, such that

the starting substrate is patterned into the semiconductor substrate, the first fin portion, and the second fin portion,

the first channel layers are respectively patterned into the first channel portions,

the first sacrificial layers are respectively patterned into first sacrificial portions,

the at least one lower channel layer and the at least one upper channel layer are respectively patterned into the at least one lower channel portion and the at least one upper channel portion,

the preformed layer is patterned into a preformed portion, and

the at least three second sacrificial layers are respectively patterned into at least three second sacrificial portions;

replacing the preformed portion with the middle isolation portion; and

removing the first sacrificial portions and the at least three second sacrificial portions.

6 . The method as claimed in claim 5 , wherein the preformed layer has a thickness greater than a thickness of each of the first channel layers.

7 . The method as claimed in claim 5 , wherein

the two first source/drain portions are respectively formed in the two first source/drain recesses,

each of the two lower source/drain portions is formed in a lower region of a corresponding one of the two second source/drain recesses, and

each of the two upper source/drain portions is formed in an upper region of a corresponding one of the two second source/drain recesses.

8 . The method as claimed in claim 5 , wherein

the first channel layers in the first lamination structure, and the at least one lower channel portion and the at least one upper channel portion in the second lamination structure are made of a first semiconductor material,

the first sacrificial layers in the first lamination structure, and the at least three second sacrificial layers are made of a second semiconductor material,

the preformed layer is made of a third semiconductor material, and

the first semiconductor material, the second semiconductor material, and the third semiconductor material have chemical compositions different from one another.

9 . The method as claimed in claim 8 , wherein

an atomic percentage of germanium in the third semiconductor material is greater than an atomic percentage of germanium in the second semiconductor material, and

an atomic percentage of germanium in the second semiconductor material is greater than an atomic percentage of germanium in the first semiconductor material.

10 . The method as claimed in claim 1 , wherein

the two first source/drain portions are spaced apart from each other along a first direction, and

a length of the middle isolation portion in the first direction is the same as a length of each of the at least one lower channel portion and the at least one upper channel portion in the second stack in the first direction.

11 . The method as claimed in claim 10 , wherein a thickness of the middle isolation portion in a second direction normal to a top surface of the semiconductor substrate is greater than a thickness of each of the at least one lower channel portion and the at least one upper channel portion in the second stack in the second direction, the second direction being different from the first direction.

12 . The method as claimed in claim 10 , wherein a thickness of the middle isolation portion in a second direction normal to a top surface of the semiconductor substrate is greater than a thickness of each of the at least one lower channel portion, the at least one upper channel portion and the middle channel portion in the first stack in the second direction, the second direction being different from the first direction.

13 . The method as claimed in claim 1 , wherein an upper surface of an uppermost one of the at least one upper channel portion in the first stack is flush with an upper surface of an uppermost one of the at least one upper channel portion in the second stack.

14 . A method for manufacturing a semiconductor structure, comprising:

forming a first fin portion and a second fin portion on a substrate;

forming an isolation region on the substrate, the first fin portion and the second fin portion being separated from each other by the isolation region;

forming a first stack on the first fin portion, the first stack including first channel portions and first sacrificial portions which are disposed to alternate with the first channel portions;

forming a second stack on the second fin portion, the second stack including

a lower channel portion,

an upper channel portion,

a preformed portion which is disposed between the lower channel portion and the upper channel portion, and

second sacrificial portions each of which is disposed between two adjacent ones of the lower channel portion, the upper channel portion, and the preformed portion;

removing the preformed portion in the second stack to form a gap between two corresponding adjacent ones of the second sacrificial portions;

forming a middle isolation portion in the gap;

forming two first source/drain portions on the first fin portion, the two first source/drain portions being spaced apart from each other such that each of the lower channel portion, the upper channel portion and the middle channel portion in the first stack extends between the two first source/drain portions;

forming two lower source/drain portions on the second fin portion, the two lower source/drain portions being spaced apart from each other such that the lower channel portion in the second stack extends between the two lower source/drain portions; and

forming two upper source/drain portions which are respectively above and spaced apart from the two lower source/drain portions such that the upper channel portion in the second stack extends between the two upper source/drain portions.

15 . The method as claimed in claim 14 , further comprising:

after formation of the two lower source/drain portions and before formation of the two upper source/drain portions, forming two isolation structures respectively on the two lower source/drain portions.

16 . The method as claimed in claim 15 , further comprising:

before formation of the two upper source/drain portions, etching back the two isolation structures to respectively expose two side surfaces of the upper channel portion in the second stack, such that the two upper source/drain portions respectively interface the two side surfaces of the upper channel portion.

17 . The method as claimed in claim 15 , wherein the two isolation structures are located at two opposite sides of the middle isolation portion, and interface the middle isolation portion.

18 . The method as claimed in claim 14 , further comprising:

removing the first sacrificial portions in the first stack;

forming a first gate dielectric around the first channel portions in the first stack;

forming a first gate electrode on the first gate dielectric;

removing the second sacrificial portions in the second stack;

forming a second gate dielectric around the lower channel portion, the upper channel portion, and the middle isolation portion in the second stack; and

forming a second gate electrode on the second gate dielectric.

19 . The method as claimed in claim 18 , wherein formation of the second gate electrode includes

forming a lower gate part on a lower portion of the second gate dielectric,

forming an isolation feature on the lower gate part, and

forming an upper gate part on an upper portion of the second gate dielectric and the isolation feature, such that the upper gate part is separated from the lower gate part by the isolation feature.

20 . The method as claimed in claim 19 , wherein the isolation feature interfaces the second gate dielectric.