IP Library Granted Patent US 12,635,530
Granted Patent B2
US 12,635,530 · App. 17/707,523 · Granted May 19, 2026

Electronic device substrate having a passive electronic component

Inventors: Numair Ahmed (Chandler, AZ); Cary Kuliasha (Mesa, AZ); Kyu Oh Lee (Chandler, AZ); Jung Kyu Han (Chandler, AZ)
Assignee: Intel Corporation
H10W44/501H10D1/20H10W70/095H10W70/635H10W70/65
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Quick Facts
Patent No.
US 12,635,530
App. No.
17/707,523
Granted
May 19, 2026
Kind
B2
Abstract

A substrate for an electronic device may include a core. The substrate may include a passive electronic component. For instance, the substrate may include a continuous layer of molding material encapsulating the passive electronic component within the core. One or more through vias may extend between a first surface of the core and a second surface of the core. The substrate may include one or more layers coupled with the core. One or more component terminals may facilitate electrical communication between the passive electronic component and one or more of the first layer or the second layer.

Claims (46)

1 . A substrate for an electronic device, the substrate comprising:

a core having a first surface and a second surface, the core including:

a passive electronic component within a continuous layer of molding material, the passive electronic component including one or more component terminals;

one or more through vias extending between the first surface of the core and the second surface of the core;

a first layer coupled with the first surface of the core at a first interface; and

a second layer coupled with the second surface of the core at a second interface,

wherein the one or more component terminals facilitate electrical communication between the passive electronic component and one or more of the first layer or the second layer, and wherein the continuous layer of molding material has a first grain structure and the first layer has a second grain structure, the second grain structure different from the first grain structure.

2 . The substrate of claim 1 , wherein the core is a discrete unit with the first layer and second layer on opposing sides of the core.

3 . The substrate of claim 1 , wherein the one or more component terminals comprise a terminal surface and the terminal surface is coplanar with one or more of the first surface or the second surface of the core.

4 . The substrate of claim 1 , wherein:

the one or more component terminals include a first component terminal and a second component terminal; and

the passive electronic component includes a central section coupled with the first component terminal and the second component terminal.

5 . The substrate of claim 4 , wherein the passive electronic component comprises an inductor.

6 . The substrate of claim 5 , wherein the central section of the passive electronic component comprises a magnetic material.

7 . The substrate of claim 1 , wherein the one or more through vias are included in a discrete via array, the discrete via array having a dielectric material coupled with the one or more through vias.

8 . The substrate of claim 7 , wherein the continuous layer of molding material is coupled with the dielectric material of the discrete via array at a third interface.

9 . The substrate of claim 8 , wherein the dielectric material of discrete via array has a third grain structure, and the third grain structure different from the first grain structure.

10 . The substrate of claim 1 , wherein the passive electronic component comprises one or more of an inductor, a capacitor, or a resistor.

11 . A process of fabricating a substrate for an electronic device, the process comprising:

providing a core having a first surface and a second surface, the core including an electronic component within a continuous layer of an insulator material, wherein the electronic component includes one or more terminals;

providing one or more vias extending between the first surface of the core and the second surface of the core;

providing a first layer coupled with the first surface of the core at a first interface; and

providing a second layer coupled with the second surface of the core at a second interface,

wherein the continuous layer of the insulator material has a first grain structure, the first layer has a second grain structure, and the second grain structure different from the first grain structure.

12 . The process of claim 11 , wherein the insulator material is continuous between at least one of the one or more vias and the electronic component.

13 . The process of claim 11 , wherein the one or more vias are included in a discrete via array, the discrete via array including a dielectric material coupled to the one or more vias, and wherein the insulator material is continuous between the passive electronic component and the dielectric material of the discrete via array.

14 . The process of claim 13 , wherein:

the dielectric material of the discrete via array has a third grain structure different from the first grain structure.

15 . The process of claim 13 , wherein the one or more vias are part of a discrete via array, and the discrete via array comprises a semiconductor material.

16 . A substrate for an electronic device, the substrate comprising:

a core having a first surface and a second surface, the core including an electronic component within a continuous layer of an insulator material, wherein the electronic component includes one or more terminals;

one or more vias extending between the first surface of the core and the second surface of the core;

a first layer coupled with the first surface of the core at a first interface; and

a second layer coupled with the second surface of the core at a second interface;

wherein the continuous layer of the insulator material has a first grain structure, the first layer has a second grain structure, and the second grain structure different from the first grain structure.

17 . The substrate of claim 16 , wherein the core is a discrete unit with the first layer and second layer on opposing sides of the core.

18 . The substrate of claim 16 , wherein the one or more terminals comprise a terminal surface and the terminal surface is coplanar with one or more of the first surface or the second surface of the core.

19 . The substrate of claim 16 , wherein:

the one or more terminals include a first component terminal and a second component terminal; and

the electronic component includes a central section coupled with the first component terminal and the second component terminal.

20 . The substrate of claim 19 , wherein the electronic component comprises an inductor.

21 . The substrate of claim 20 , wherein the central section of the electronic component comprises a magnetic material.

22 . The substrate of claim 16 , wherein the one or more vias are included in a discrete via array, the discrete via array having a dielectric material coupled with the one or more vias.

23 . The substrate of claim 22 , wherein the continuous layer of the insulator material is coupled with the dielectric material of the discrete via array at a third interface.

24 . The substrate of claim 23 , wherein the dielectric material of discrete via array has a third grain structure, and the third grain structure different from the first grain structure.

25 . The substrate of claim 16 , wherein the electronic component comprises one or more of an inductor, a capacitor, or a resistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2022
From: AHMED, NUMAIR; KULIASHA, CARY; LEE, KYU OH; HAN, JUNG KYU
To: INTEL CORPORATION
Reel/Frame 059813/0437 →
Continuity (1)
Related Publication 20230317642A1 · Oct 5, 2023
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