Ball map pattern
A printed circuit board includes a grid of pads and tracks. The grid of pads includes a first pair of adjacent signal pads arranged in a first column and a second pair of adjacent signal pads arranged in a first row. A first signal pad of the second pair is arranged in the first column. The grid of pads also includes a third pair of adjacent signal pads arranged in a second row. A second signal pad of the first pair is arranged in the second row. The grid of pads further includes a fourth pair of adjacent signal pads arranged in a second column. A third signal pad of the third pair is arranged in the second column. A fourth signal pad of the fourth pair is arranged in the first row. The tracks are electrically coupled to the first, second, third, and fourth pairs.
1 . A substrate comprising:
a grid of pads comprising:
a first pair of adjacent signal pads arranged in a first column of the grid;
a second pair of adjacent signal pads arranged in a first row of the grid, wherein a first signal pad of the second pair is arranged in the first column, and wherein a second signal pad of the second pair is arranged in a second column;
a third pair of adjacent signal pads arranged in a second row of the grid, wherein a first signal pad of the first pair is arranged in the second row, and wherein a second signal pad of the third pair is arranged in a third row;
a fourth pair of adjacent signal pads arranged in a third column of the grid, wherein a first signal pad of the third pair is arranged in the third column, wherein a second signal pad of the third pair is arranged in a fourth column, wherein a first signal pad of the fourth pair is arranged in the first row, wherein a second signal pad of the fourth pair is arranged in a fourth row, and wherein the first, second, third, and fourth pairs are distinct from each other;
a first ground pad arranged adjacent to the second signal pad of the first pair in the third row and the second column;
a second ground pad arranged adjacent to the second signal pad of the second pair in the fourth row and the second column;
a third ground pad arranged adjacent to the second signal pad of the third pair in the third row and the fourth column; and
a fourth ground pad arranged adjacent to the second signal pad of the fourth pair in the fourth row and the fourth column; and
a plurality of tracks, wherein each signal pad of the first pair, the second pair, the third pair, and the fourth pair is electrically coupled to a track of the plurality of tracks.
2 . The substrate of claim 1 , wherein:
the grid of pads further comprises a fifth ground pad arranged adjacent to the first signal pad of the first pair in the second row and the second column; and
the substrate defines a first stitching via arranged between the first signal pad of the first pair and the fifth ground pad.
3 . The substrate of claim 2 , wherein the first stitching via is positioned closer to the fifth ground pad than the first signal pad of the first pair.
4 . The substrate of claim 2 , wherein the first stitching via is smaller than the fifth ground pad.
5 . The substrate of claim 2 , wherein the first stitching via and the fifth ground pad are electrically coupled to ground.
6 . The substrate of claim 2 , wherein a second fifth signal pad of the second pair is arranged in the second column.
7 . The substrate of claim 2 , wherein:
the substrate further defines a second stitching via arranged between the second signal pad of the first pair and the first ground pad.
8 . The substrate of claim 2 , wherein the first stitching via is smaller than the first signal pad of the first pair.
9 . The substrate of claim 1 , wherein the substrate further defines a plurality of stitching vias forming an isolation barrier between the first pair and the second pair and between the third pair and the fourth pair.
10 . The substrate of claim 1 , wherein the first pair of adjacent signal pads and the second pair of adjacent signal pads form an L-shape.
11 . An integrated circuit package comprising:
a ball grid array comprising:
a first pair of adjacent signal solder balls arranged in a first column;
a second pair of adjacent signal solder balls arranged in a first row, wherein a first signal solder ball of the second pair is arranged in the first column, and wherein a second signal solder ball of the second pair is arranged in a second column;
a third pair of adjacent signal solder balls arranged in a second row, wherein a first signal solder ball of the first pair is arranged in the second row, and wherein a second signal solder ball of the third pair is arranged in a third row;
a fourth pair of adjacent signal solder balls arranged in a third column, wherein a first signal solder ball of the third pair is arranged in the third column, wherein a second signal solder ball of the third pair is arranged in a fourth column, wherein a first signal solder ball of the fourth pair is arranged in the first row, wherein a second signal solder ball of the fourth pair is arranged in a fourth row, and wherein the first pair of adjacent signal solder balls, the second pair of adjacent signal solder balls, the third pair of adjacent signal solder balls, and the fourth pair of adjacent signal solder balls are distinct from each other;
a first ground solder ball arranged adjacent to the second signal solder ball of the first pair in the third row and the second column;
a second ground solder ball arranged adjacent to the second signal solder ball of the second pair in the fourth row and the second column;
a third ground solder ball arranged adjacent to the second signal solder ball of the third pair in the third row and the fourth column; and
a fourth ground solder ball arranged adjacent to the second signal solder ball of the fourth pair in the fourth row and the fourth column; and
a metal layer electrically coupled to the first pair of adjacent signal solder balls, the second pair of adjacent signal solder balls, the third pair of adjacent signal solder balls, and the fourth pair of adjacent signal solder balls.
12 . The integrated circuit package of claim 11 , wherein the first pair of adjacent signal solder balls and the second pair of adjacent signal solder balls form an L-shape.
13 . A system comprising:
a printed circuit board comprising:
a first pair of signal pads arranged in a first column of a grid of pads;
a second pair of signal pads arranged in a first row of the grid of pads, wherein a first signal pad of the second pair is arranged in the first column, and wherein a second signal pad of the second pair is arranged in a second column of the grid of pads;
a third pair of signal pads arranged in a second row of the grid of pads, wherein a first signal pad of the first pair is arranged in the second row, and wherein a second signal pad of the third pair is arranged in a third row of the grid of pads;
a fourth pair of signal pads arranged in a third column of the grid of pads, wherein a first signal pad of the third pair is arranged in the third column, wherein a second signal pad of the third pair is arranged in a fourth column of the grid of pads, wherein a first signal pad of the fourth pair is arranged in the first row, wherein a second signal pad of the fourth pair is arranged in a fourth row of the grid of pads, and wherein the first, second, third, and fourth pairs are distinct from each other;
a first ground pad arranged adjacent to the second signal pad of the first pair in the third row and the second column;
a second ground pad arranged adjacent to the second signal pad of the second pair in the fourth row and the second column;
a third ground pad arranged adjacent to the second signal pad of the third pair in the third row and the fourth column; and
a fourth ground pad arranged adjacent to the second signal pad of the fourth pair in the fourth row and the fourth column; and
an integrated circuit package comprising a ball grid array electrically coupled to the first pair, the second pair, the third pair, and the fourth pair.
14 . The system of claim 13 , wherein:
the printed circuit board further comprises a fifth ground pad arranged adjacent to the first signal pad of the first pair in the second row and the second column; and
the printed circuit board defines a first stitching via arranged between the first signal pad of the first pair and the fifth ground pad.
15 . The system of claim 14 , wherein the first stitching via is positioned closer to the fifth ground pad than the first signal pad of the first pair.
16 . The system of claim 14 , wherein the first stitching via is smaller than the fifth ground pad.
17 . The system of claim 14 , wherein the first stitching via and the fifth ground pad are electrically coupled to ground.
18 . The system of claim 14 , wherein a second fifth signal pad of the second pair is arranged in the second column.