Granted Patent B2

US 12,639,222 · App. 18/817,421 · Granted May 26, 2026

Inventor: David Michael Bull (Cambridge, GB)

Assignee: Arm Limited

G06F12/0802G06F12/12

Abstract

Claims (53)

1 . An apparatus comprising:

control information storage configured to store a plurality of entries of control information for controlling data processing operations relating to a given memory address;

eviction storage configured to store a plurality of entries that have been evicted from the control information storage;

lookup handling circuitry configured to control handling of a lookup request for data corresponding to a target memory address, wherein:

in a parallel mode, the lookup handling circuitry is configured to control the control information storage and the eviction storage to perform the lookup request in parallel; and

in a serial mode, the lookup handling circuitry is configured to control the control information storage to perform the lookup request, and to control the eviction storage to perform the lookup request in response to the lookup request missing in the control information storage; and

mode control circuitry configured to control whether the lookup handling circuitry is to operate in the parallel mode or the serial mode.

2 . The apparatus of claim 1 , wherein the mode control circuitry is configured to maintain a utilisation metric indicative of a utilisation of the control information storage and the eviction storage and to control whether the lookup handling circuitry is to operate in the parallel mode or the serial mode in dependence on the utilisation metric.

3 . The apparatus of claim 2 , wherein the mode control circuitry is configured to monitor a number of hits in the control information storage and the eviction storage during a predetermined sample period and to set the utilisation metric based on the number of hits.

4 . The apparatus of claim 2 , wherein the mode control circuitry comprises tracking circuitry configured to track the utilisation of the control information storage and the eviction storage based on at least one bitmap representative of the plurality of entries in the control information storage and the plurality of entries in the eviction storage.

5 . The apparatus of claim 4 , wherein

the tracking circuitry is responsive to a hit signal indicative of a given entry in the control information storage or the eviction storage to set a corresponding bit in the bitmap; and

in response to expiry of a predetermined sample period, the mode control circuitry is configured to set the utilisation metric based on the number of set bits in the bitmap.

6 . The apparatus of claim 1 , wherein, at least in the serial mode, the mode control circuitry is configured to maintain an eviction storage hit rate metric indicative of a fraction of lookup requests in the eviction storage that detect a hit, and to control whether the lookup handling circuitry is to operate in the parallel mode or the serial mode in dependence on the eviction storage hit rate metric.

7 . The apparatus of claim 6 , wherein

the mode control circuitry comprises a counter, the value of the counter being indicative of the number of hits in the eviction storage; and

the mode control circuitry is configured to reset the counter upon expiry of a predetermined sampling period.

8 . The apparatus of claim 6 , wherein the mode control circuitry comprises history storage circuitry configured to store a hit history indicative of entries that have been hit in the eviction storage.

9 . The apparatus of claim 8 , wherein the history storage circuitry is configured to allocate hit data indicative of a given entry in response to a first hit on the given entry during a predetermined sampling period.

10 . The apparatus of claim 1 , wherein the mode control circuitry is configured to control the lookup handling circuitry to switch from the serial mode to the parallel mode in response to an activation metric satisfying an activation condition; and

the mode control circuitry is configured to control the lookup handling circuitry to switch from the parallel mode to the serial mode in response to a deactivation metric satisfying a deactivation condition.

11 . The apparatus of claim 10 , wherein

the mode control circuitry is configured to determine that the activation condition is satisfied based on a comparison of the activation metric with an activation threshold; and

the mode control circuitry is configured to determine that the deactivation condition is satisfied based on a comparison of the deactivation metric with a deactivation threshold.

12 . The apparatus of claim 10 , wherein the mode control circuitry is configured to set the activation condition to be more easily satisfied than the deactivation condition.

13 . The apparatus of claim 1 , wherein the mode control circuitry is responsive to an occurrence of a context switch to cause the lookup handling circuitry to operate in the serial mode.

14 . The apparatus of claim 1 , wherein the eviction storage is configured to have one or more of:

a larger capacity than the control information storage; and

a different indexing scheme than the control information storage.

15 . The apparatus of claim 1 , comprising result combination circuitry configured to, while the lookup handling circuitry is operating in the parallel mode, receive a first lookup result from the control information storage and a second lookup result from the eviction storage, and to generate a final lookup result as a response to the lookup request.

16 . The apparatus of claim 1 , wherein the control information storage is any one of:

a memory address translation cache;

a prediction cache.

17 . A system comprising:

the apparatus of claim 1 , implemented in at least one packaged chip;

at least one system component;

and a board,

wherein the at least one packaged chip and the at least one system component are assembled on the board.

18 . A chip-containing product comprising the system of claim 17 , wherein the system is assembled on a further board with at least one other product component.

19 . A method comprising:

storing, in control information storage, a plurality of entries of control information for controlling data processing operations relating to a given memory address;

storing, in eviction storage, a plurality of entries that have been evicted from the control information storage;

controlling handling of a lookup request for data corresponding to a target memory address, wherein:

in a parallel mode, controlling the control information storage and the eviction storage to perform the lookup request in parallel; and

in a serial mode, controlling the control information storage to perform the lookup request, and to control the eviction storage to perform the lookup request in response to the lookup request missing in the control information storage; and

controlling whether the lookup handling circuitry is to operate in the parallel mode or the serial mode.

20 . An apparatus comprising:

a cache configured to store a plurality of entries of data;

an eviction cache to store a plurality of entries that have been evicted from the cache;

lookup handling circuitry configured to control handling of a lookup request for data corresponding to a target memory address, wherein:

in a parallel mode, the lookup handling circuitry is configured to control the cache and the eviction cache to perform the lookup request in parallel; and

in a serial mode, the lookup handling circuitry is configured to control the cache to perform the lookup request, and to control the eviction cache to perform the lookup request in response to the lookup request missing in the cache; and

mode control circuitry configured to control whether the lookup handling circuitry is to operate in the parallel mode or the serial mode.

Assignments (1)

Continuity (1)

References Cited (10)