Bit line voltage clamping read circuit for an in- memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.
1 . An in-memory computation circuit, comprising:
a memory array including memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a true bit line connected to the memory cells of the column and a false bit line connected to the memory cells of the column;
a word line driver circuit for each row having an output connected to drive the word line of the row;
a row controller circuit configured to simultaneously actuate the word lines by applying pulses through the word line driver circuits to the word lines in response to feature data for an in-memory compute operation; and
a column processing circuit including a true first read circuit coupled to each true bit line and a false read circuit coupled to each false bit line,
wherein each true read circuit comprises:
a first differential amplifier having a first input coupled to the true bit line, a second input configured to receive a reference voltage, and an output;
wherein said reference voltage is at a level greater than a write margin voltage for the memory cells where the memory cells risk inadvertent bit flip during the simultaneous actuation of the word lines for the in-memory compute operation;
a first MOS transistor having a drain coupled to the true bit line to receive a first read current and a gate coupled to the output of the first differential amplifier;
a second MOS transistor having a gate coupled to the output of the first differential amplifier and a drain configured to output a first mirrored read current; and
a first integration capacitor configured to integrate the first mirrored read current to generate a first output voltage, and
wherein each false read circuit comprises:
a second differential amplifier having a first input coupled to the false bit line, a second input configured to receive said reference voltage, and an output;
a third MOS transistor having a drain coupled to the false bit line to receive a second read current and a gate coupled to the output of the second differential amplifier; and
a fourth MOS transistor having a gate coupled to the output of the second differential amplifier and a drain configured to output a second mirrored read current; and
a second integration capacitor configured to integrate the second mirrored read current to generate a second output voltage.
2 . The circuit of claim 1 :
wherein the first differential amplifier and first MOS transistor function to clamp a voltage on the true bit line to said reference voltage; and
wherein the second differential amplifier and third MOS transistor function to clamp a voltage on the false bit line to said reference voltage.
3 . The circuit of claim 1 , wherein said column processing circuit further comprises an analog-to-digital converter (ADC) circuit configured to convert a difference between the first and second output voltages to a digital output.
4 . The circuit of claim 1 , further comprising a switch coupled in series with each of the second and fourth MOS transistors, wherein said switch is actuated by an integration control signal to control integration of the first and second mirrored read currents by the first and second integration capacitors, respectively, during the in-memory compute operation.
5 . The circuit of claim 1 , wherein said first and second integration capacitors are discharged in response to assertion of a reset control signal at a beginning of the in-memory compute operation.
6 . The circuit of claim 1 , wherein the word line driver circuit is powered by an adaptive supply voltage, and further comprising:
a voltage generator circuit configured to generate the adaptive supply voltage for powering the word line driver circuits during the simultaneous actuation of the word lines for the in-memory compute operation, said adaptive supply voltage having a level which is dependent on integrated circuit process and/or temperature conditions.
7 . The circuit of claim 6 , wherein the voltage generator circuit comprises:
a current source configured to generate a current applied to a first node; and
a series connection of a first transistor and second transistor between the first node and a reference node;
wherein the adaptive supply voltage is generated at said first node;
wherein the first transistor is a replica of a passgate transistor within the memory cell; and
wherein the second transistor is a replica of a pull down transistor within the memory cell.
8 . The circuit of claim 7 , wherein:
the current generated by the current source has a magnitude set as a function of a reference current representative of current flowing through the passgate transistor and the pull down transistor for an applicable integrated circuit process corner;
the magnitude of the current generated by the current source is scaled by a factor applied to the reference current;
the first transistor is scaled by said factor for the replica of the passgate transistor; and
the second transistor is scaled by said factor for the replica of the pull down transistor.
9 . The circuit of claim 8 , wherein said column processing circuit further comprises a successive approximation register (SAR) type analog-to-digital converter (ADC) circuit configured to convert the first output voltage to a digital output, said SAR type ADC circuit including a feedback current digital-to-analog converter (DAC) circuit having selectively actuated current sources referenced to said reference current.
10 . The circuit of claim 7 , further comprising an amplifier circuit having an input coupled to said first node and an output coupled to power the word line driver circuits.
11 . The circuit of claim 7 , wherein the current source is controlled to generate an adjustment to the current, and further comprising a control circuit configured to generate a control signal for application to the current source for modulating a level of the current away from a nominal level in response to an applicable integrated circuit process corner for transistor devices of the memory cells.
12 . The circuit of claim 11 , wherein the applicable integrated circuit process corner is indicated by a programmed code stored in the control circuit.
13 . The circuit of claim 12 , wherein the control circuit includes a lookup table (LUT) correlating the programmed code to a value of the control signal.
14 . The circuit of claim 11 , wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to cause a temperature dependent tuning of the level of the current set in response to the applicable integrated circuit process corner.
15 . The circuit of claim 14 , wherein the control circuit includes a lookup table (LUT) correlating a sensed integrated circuit temperature to a tuning level for the value of the control signal.
16 . The circuit of claim 1 , wherein each memory cell is a 6T SRAM cell.