Amplitude modulation for writing to a multi-level bit-cell
An apparatus comprising a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line. The apparatus further comprises a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, and wherein the capacitor includes at least four stable states. In at least one example, the capacitor has a first polarization loop and a second polarization loop, wherein the second polarization loop is within the first polarization loop.
1 . A method comprising:
voltage boosting a word-line above a nominal voltage to generate a boosted word-line, wherein the boosted word-line has a first pulse, wherein the word-line is coupled to a gate terminal of a transistor, wherein the transistor is further coupled to a bit-line, wherein the transistor is coupled to a capacitor, and wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor; and
writing a first state and a second state to the capacitor in a first write phase via amplitude modulation of the bit-line and by asserting the plate-line between a first pulse of the word-line to generate an asserted plate-line, wherein the asserted plate-line has a second pulse shorter than the first pulse.
2 . The method of claim 1 , wherein the plate-line is parallel to the word-line and orthogonal to the bit-line.
3 . The method of claim 1 , wherein writing the first state includes:
setting, after the asserted plate-line is generated and between the second pulse, the bit-line to a ground voltage to write the first state to the capacitor.
4 . The method of claim 1 , wherein writing the second state includes:
setting, after the asserted plate-line is generated, the bit-line to a voltage level between a nominal voltage level and a ground voltage to write the second state to the capacitor; and
asserting the bit-line between a duration of the second pulse after setting the bit-line to the ground voltage.
5 . The method of claim 1 further includes writing a third state and a fourth state in a second write phase by de-asserting the plate-line or setting the plate-line to a ground voltage.
6 . The method of claim 5 , wherein the first write phase is before the second write phase, or wherein the second write phase is before the first write phase.
7 . The method of claim 5 , wherein writing the third state includes:
asserting, after the plate-line is de-asserted or set to the ground voltage and between a duration of the first pulse, the bit-line to a voltage between a nominal voltage level and a ground voltage for a duration of a third pulse to write the third state to the capacitor, wherein the third pulse is shorter than the first pulse, and wherein the duration of the third pulse is within a duration of the first pulse.
8 . The method of claim 5 , wherein writing the fourth state includes:
asserting, after the plate-line is de-asserted or set to the ground voltage and between a duration of the first pulse, the bit-line to a nominal voltage level for a duration of a fourth pulse, wherein the fourth pulse is de-asserted prior to de-asserting the first pulse.
9 . The method of claim 5 , wherein the capacitor has a first polarization loop and a second polarization loop, and wherein the second polarization loop is within the first polarization loop.
10 . The method of claim 9 , wherein the first state and the fourth state are part of the first polarization loop, and wherein the second state and the third state are part of the second polarization loop.
11 . The method of claim 5 further includes writing the fourth state prior to writing the first state or the second state.
12 . The method of claim 5 further includes writing the first state prior to writing the third state or the fourth state.
13 . The method of claim 1 , wherein the capacitor includes:
a first capacitor with a first non-linear polar material; and
a second capacitor with a second non-linear polar material, wherein the first capacitor is coupled in parallel to the second capacitor.
14 . The method of claim 13 , wherein the first non-linear polar material has a different thickness than the second non-linear polar material, and wherein first non-linear polar material has same doping as the second non-linear polar material.
15 . The method of claim 13 , wherein the first non-linear polar material has a different doping than the second non-linear polar material, and wherein first non-linear polar material has a same thickness as the second non-linear polar material.
16 . The method of claim 13 , wherein the capacitor further includes a resistive device coupled in series with the second capacitor, and wherein the resistive device and the second capacitor in combination are parallel to the first capacitor.
17 . The method of claim 13 , wherein the first capacitor has a first polarization loop, and wherein the second capacitor has a second polarization loop which is different from the first polarization loop.
18 . The method of claim 13 , wherein the first non-linear polar material or the second non-linear polar material includes:
a form ABB′O 3 , wherein “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein “B” includes one of Mn, Fe, Ta, or Nb, and wherein “B′” includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
a form AA′BO 3 , wherein “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein “B” includes one of Mn, Fe, Ta, or Nb, wherein “A” includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, and wherein A′ comprises a valency of site A, but different ferroelectric polarizability from A;
a form ABO 3 , wherein “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, and wherein “B” includes one of Mn, Fe, Ta, or Nb;
bismuth ferrite (BFO), BFO with a first doping material, wherein the first doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of 3d, 4d, 5d, 6d, 4f, or 5f series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , KNbO 3 , NaTaO 3 , wherein the perovskite material is doped with La or lanthanides, chemically substituted lead titanate, and wherein Zr, La, or Nb is substituted in Ti site;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a BaTiO 3 (BTO) based relaxor which includes one of: BaTiO 3 —Bi (Zn 1/2 Ti 1/2 )O 3 (BTO-BZT), BaTiO 3 —BiScO 3 (BTO-BS): BiScO 3 , Ba (1-x) Sr x TiO 3 (BST), BaTiO 3 —Pb(Mg 1/3 Nb 2/3 )O 3 (BTO-PMN), BaTi (1-x) Zr x O 3 (BTZ), BaTiO 3 —Pb(Zn 1/3 Nb 2/3 )O 3 (BTO-PZN), BaTiO 3 —Pb(Sc 1/2 Nb 1/2 )O 3 (BTO-PSN);
a PZT based relaxor which includes one of: PZT-Pb(Mg 1/3 Nb 2/3 )O 3 (PZT-PMN), PZT-Pb(Ni 1/3 Nb 2/3 )O 3 (PZT-PNN), PZT-Pb(Zn 1/3 Nb 2/3 )O 3 (PZT-PZN), PZT-Pb(Sc 1/2 Nb 1/2 )O 3 (PZT-PSN), PZT-Pb(Fe 1/2 Nb 1/2 )O 3 (PZT-PFN), PZT-Pb(La,Zr,Ti)O 3 (PZT-PLZT), or PZT-Pb(Ti,Mn)O 3 (PZT-PTM);
a SrBi 2 Ta 2 O 9 (SBT) based relaxor which includes one of: paraelectric SBT-SrBi 2 (Nb,Ta) 2 O 9 (SBT-SBNT), or SBT doped with one of: Mn, Fe, Co, La, Ce or Nd, Ba, or Ca;
a first hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
a second hexagonal ferroelectric of a type RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
lithium niobate, lithium tantalate, lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate;
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100;
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides of a form Hf (1-x) E x O y , where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein ‘x’ and ‘y’ are first and second fractions, respectively;
HfO 2 doped with one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) Nor Al (1-x-y) Mg (x) Nb (y) N, wherein ‘x’ and ‘y’ are third and fourth fractions, respectively; or
LiNbO 3 , LiTaO 3 , LiTaO 2 F 2 , Sr (x) Ba (1-x) Nb 2 O 6 where 0.32≤x≤0.8, or KSr 2 Nb 5 O 15 ; or
a paraelectric material comprising SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, or La-substituted PbTiO 3 .
19 . An apparatus comprising:
a first circuitry to voltage boost a word-line above a nominal voltage to generate a boosted word-line, wherein the boosted word-line has a first pulse width, wherein the word-line is coupled to a gate terminal of a transistor, wherein the transistor is further coupled to a bit-line, wherein the transistor is coupled to a capacitor, and wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor; and
a second circuitry to write a first state and a second state to the capacitor in a first write phase via amplitude modulation of the bit-line and by assertion of the plate-line between a duration of a first pulse of the word-line to generate an asserted plate-line, wherein the asserted plate-line has a second pulse shorter than the first pulse.
20 . The apparatus of claim 19 , wherein the second circuitry is to set, after the asserted plate-line is generated and between a duration of the second pulse, the bit-line to a ground voltage to write the first state to the capacitor, and wherein the second circuitry is to:
set, after the asserted plate-line is generated, the bit-line to a voltage level between a nominal voltage level and a ground voltage to write the second state to the capacitor; and
assert the bit-line between the duration of the second pulse after setting the bit-line to the ground voltage.