Granted Patent B2

US 12,641,722 · App. 18/699,544 · Granted May 26, 2026

Inventors: Han Sang Kim (Seoul, KR); Bo Ra Kang (Seoul, KR); Yong Suk Kim (Seoul, KR)

Assignee: LG INNOTEK CO., LTD.

H05K1/115H01L23/49822H01L23/49838H01L23/49894H05K1/0256H05K2201/032H05K2201/09563

Abstract

Claims (56)

1 . A circuit board comprising:

a first insulating layer including a through hole passing through an upper surface and a lower surface opposite to the upper surface;

a coating layer disposed on an inner wall of the through hole of the first insulating layer; and

a through electrode disposed to fill the through hole on the coating layer,

wherein the through electrode layer includes:

a first metal layer disposed on the coating layer; and

a second metal layer disposed on the first metal layer,

wherein the coating layer includes:

a first functional group bonded to the first insulating layer; and

a second functional group bonded to the first metal layer,

wherein the first insulating layer includes a hydroxyl (OH) group, and

wherein the first functional group of the coating layer includes at least one of a carboxyl group (COOH) and CH 3 bonded to the hydroxyl group, and

wherein the second functional group of the coating layer includes at least one of nitrogen (N) and sulfur (S) coordinated with the first metal layer.

2 . The circuit board of claim 1 , wherein:

the first metal layer is an electroless plating layer, and

the second metal layer is an electrolytic plating layer formed with the first metal layer as a seed layer.

3 . The circuit board of claim 2 , wherein the second functional group of the coating layer coordinates with a catalyst metal of the first metal layer.

4 . The circuit board of claim 3 , wherein:

the catalyst metal of the first metal layer includes palladium, and

at least one of nitrogen (N) and sulfur (S) of the second functional group of the coating layer coordinates with the palladium.

5 . The circuit board of claim 1 , wherein the first metal layer has a thickness ranging between 1 um and 2.5 um.

6 . The circuit board of claim 5 , wherein a centerline average roughness value (Ra) of a surface of the first metal layer satisfies a range between 200 nm and 600 nm, and

wherein a maximum section height value (Rt) of the surface of the first metal layer satisfies a range between 2 um and 6 um.

7 . The circuit board of claim 1 , further comprising:

a circuit pattern layer disposed on the first insulating layer,

wherein the coating layer further includes a region extending from a portion disposed on the inner wall of the through hole and disposed between the first insulating layer and the circuit pattern layer.

8 . The circuit board of claim 7 , wherein the circuit pattern layer includes:

a third metal layer disposed on the region of the coating layer; and

a fourth metal layer disposed on the third metal layer.

9 . The circuit board of claim 8 , wherein the region of the coating layer in contact with the third metal layer includes:

a first functional group including at least one of a carboxyl group (COOH) and CH 3 bonded to a hydroxyl group, and

at least one second functional group of nitrogen (N) and sulfur (S) that coordinates with a catalyst metal of the third metal layer.

10 . The circuit board of claim 8 , wherein the region of the coating layer includes:

an overlapping region vertically overlapping the circuit pattern layer; and

a non-overlapping region excluding the overlapping region.

11 . The circuit board of claim 10 , further comprising:

a second insulating layer disposed on the first insulating layer, and

wherein the overlapping region of the coating layer is in contact with the circuit pattern layer, and

wherein the non-overlapping region of the coating layer is in contact with the second insulating layer.

12 . A semiconductor package comprising:

an insulating layer having a through hole passing through an upper surface and a lower surface opposite to the upper surface;

a coating layer including a first portion disposed on the upper surface of the insulating layer and a second portion disposed on an inner wall of the through hole;

a circuit pattern layer disposed on the first portion of the coating layer; and

a through electrode disposed on the second portion of the coating layer to fill the through hole,

wherein the circuit pattern layer and the through electrode includes:

a first metal layer disposed on the first and second portions of the coating layer; and

a second metal layer disposed on the first metal layer, and

wherein the coating layer includes:

a first functional group bonded to the first insulating layer; and

a second functional group bonded to the first metal layer,

wherein the first insulating layer includes a hydroxyl (OH) group, and

wherein the first functional group of the coating layer includes at least one of a carboxyl group (COOH) and CH 3 bonded to the hydroxyl group, and

wherein the second functional group of the coating layer includes at least one of nitrogen (N) and sulfur (S) coordinated with the first metal layer.

13 . The semiconductor package of claim 12 , wherein the second functional group of the coating layer coordinates with a catalyst metal of the first metal layer.

14 . The semiconductor package of claim 13 , wherein the catalyst metal of the first metal layer includes palladium, and

wherein at least one of nitrogen (N) and sulfur (S) of the second functional group of the coating layer is coordinated with the palladium.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (17)