Semiconductor device including ferroelectric layer and method of manufacturing the same
A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure each extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a ferroelectric layer disposed on the semiconductor layer and including a ferroelectric superlattice structure, and a gate electrode layer disposed on the ferroelectric layer.
1 . A semiconductor device comprising:
a substrate;
a bit line structure and a source line structure each extending in a direction perpendicular to a surface of the substrate;
a semiconductor layer disposed over the substrate between the bit line structure and the source line structure on a plane parallel to the surface of the substrate;
a ferroelectric layer disposed on the semiconductor layer and including a ferroelectric superlattice structure; and
a gate electrode layer disposed on the ferroelectric layer,-
wherein the semiconductor layer, the ferroelectric layer and the gate electrode layer are stacked along the direction perpendicular to the surface of the substrate.
2 . The semiconductor device of claim 1 , wherein the ferroelectric superlattice structure includes a plurality of two-dimensional nanosheets.
3 . The semiconductor device of claim 1 , wherein the ferroelectric superlattice structure includes alternately stacked first and second metal oxide nanosheets, the first metal oxide nanosheet and the second metal oxide nanosheet being different from each other.
4 . The semiconductor device of claim 3 ,
wherein the first metal oxide nanosheet includes a two-dimensional material having formula of AB 2 O 7 , and
wherein the second metal oxide nanosheet includes a two-dimensional material having formula of C 2 B 3 O 10
(Here, element A is lanthanum (La) or europium (Eu), element B is niobium (Nb) or tantalum (Ta), element C is calcium (Ca) or strontium (Sr), and element O is oxygen).
5 . The semiconductor device of claim 3 , wherein each of the first and second metal oxide nanosheets includes metal oxide selected from the group consisting of titanium oxide, calcium niobium oxide, manganese oxide, niobium oxide, tantalum oxide, and titanium niobium oxide.
6 . The semiconductor device of claim 3 , wherein each of the first and second metal oxide nanosheets includes a perovskite material.
7 . The semiconductor device of claim 6 , wherein the perovskite material includes one selected from Ca 2 Nb 3 O 10 , Ca 2 NaNb 4 O 13 , Ca 2 Na 2 Nb 5 O 16 , and Ca 2 Na 3 Nb 6 O 19 .
8 . The semiconductor device of claim 1 , wherein the ferroelectric layer is disposed to contact the semiconductor layer.
9 . The semiconductor device of claim 1 , wherein the semiconductor layer includes:
a source region in contact with the bit line structure;
a drain region in contact with the source line structure; and
a channel region disposed between the source region and the drain region.
10 . A semiconductor device comprising:
a substrate;
a bit line structure and a source line structure each extending in a direction perpendicular to a surface of the substrate; and
a plurality of unit cell structures electrically connected to the bit line structure and the source line structure,
wherein each of the plurality of unit cell structures includes:
a semiconductor layer disposed on a plane parallel to the surface of the substrate over the substrate and in contact with the bit line structure and the source line structure;
a ferroelectric layer disposed on the semiconductor layer and including a ferroelectric superlattice structure; and
a gate electrode layer disposed to be spaced apart from the bit line structure and the source line structure on the ferroelectric layer, and
wherein the plurality of unit cell structures are disposed to be spaced apart from each other in the direction perpendicular to the surface of the substrate
wherein the semiconductor layer, the ferroelectric layer and the gate electrode layer are stacked along the direction perpendicular to the surface of the substrate.
11 . The semiconductor device of claim 10 , wherein the ferroelectric superlattice structure includes a plurality of two-dimensional nanosheets.
12 . The semiconductor device of claim 10 , wherein the ferroelectric superlattice structure includes alternately stacked first and second metal oxide nanosheets, the first metal oxide nanosheet and the second metal oxide nanosheet being different from each other.
13 . The semiconductor device of claim 12 ,
wherein the first metal oxide nanosheet includes a two-dimensional material having formula of AB 2 O 7 , and
wherein the second metal oxide nanosheet includes a two-dimensional material having formula of C 2 B 3 O 10
(Here, element A is lanthanum (La) or europium (Eu), element B is niobium (Nb) or tantalum (Ta), element C is calcium (Ca) or strontium (Sr), and element O is oxygen).
14 . The semiconductor device of claim 12 , wherein each of the first and second metal oxide nanosheets includes metal oxide selected from the group consisting of titanium oxide, calcium niobium oxide, manganese oxide, niobium oxide, tantalum oxide, and titanium niobium oxide.
15 . The semiconductor device of claim 12 , wherein each of the first and second metal oxide nanosheets includes a perovskite material.
16 . The semiconductor device of claim 15 , wherein the perovskite material includes one selected from Ca 2 Nb 3 O 10 , Ca 2 NaNb 4 O 13 , Ca 2 Na 2 Nb 5 O 16 , and Ca 2 Na 3 Nb 6 O 19 .
17 . The semiconductor device of claim 10 , wherein the ferroelectric layer is disposed to contact the semiconductor layer.
18 . The semiconductor device of claim 10 , wherein the semiconductor layer includes:
a source region in contact with the bit line structure;
a drain region in contact with the source line structure; and
a channel region disposed between the source region and the drain region.