Semiconductor device and method of manufacturing the same
An interlayer insulating film is formed on an upper surface of a semiconductor substrate. A source pad and a kelvin pad, a gate pad, and a drain pad each having a smaller plane area than a plane area of the source pad are formed on the interlayer insulating film. A first plating layer is formed on the source pad. A second plating layer is formed on each of the kelvin pad, the gate pad, and the drain pad. A material of an uppermost surface of the first plating layer is a metal other than a noble metal, and a material of an uppermost surface of the second plating layer is a noble metal.
1 . A method of manufacturing a semiconductor device, the method comprising:
(a) preparing a semiconductor substrate having an upper surface;
(b) forming an interlayer insulating film on the upper surface of the semiconductor substrate;
(c) forming a first pad and a second pad having a smaller plane area than a plane area of the first pad on the interlayer insulating film;
(d) forming a seed layer on the first pad and the second pad by a sputtering method;
(e) forming a first plating film on the seed layer on the first pad and forming a second plating film on the seed layer on the second pad by an electrolytic plating method;
(f) forming a third plating film on the second plating film by an electrolytic plating method; and
(g) forming a fourth plating film on the third plating film by an electrolytic plating method,
wherein a material forming the third plating film differs from a material forming each of the first plating film and the second plating film,
wherein a material forming the fourth plating film differs from a material forming each of the first plating film, the second plating film, and the third plating film,
wherein the material forming each of the first plating film and the second plating film is a metal other than a noble metal,
wherein the material forming the fourth plating film is a noble metal,
wherein the method further comprises (h) between the (a) and the (b), forming a MOSFET in the semiconductor substrate,
wherein the (c) includes:
(c4) forming a first wiring and a second wiring on the interlayer insulating film;
(c5) forming a first insulating film on the interlayer insulating film to cover the first wiring and the second wiring; and
(c6) forming a first opening in the first insulating film to expose a first portion of the first wiring and forming a second opening in the first insulating film to expose a second portion of the second wiring,
wherein the first pad is the first portion of the first wiring exposed in the first opening,
wherein the second pad is the second portion of the second wiring exposed in the second opening,
wherein the first pad is electrically connected to a source region of the MOSFET, and
wherein the second pad is electrically connected to a drain region of the MOSFET or a gate electrode of the MOSFET.
2 . The method according to claim 1 ,
wherein a thickness of the second plating film is greater than a thickness of each of the third plating film and the fourth plating film.
3 . The method according to claim 2 ,
wherein the material forming each of the first plating film and the second plating film is copper,
wherein the material forming the third plating film is palladium, and
wherein the material forming the fourth plating film is gold.
4 . A method of manufacturing a semiconductor device, the method comprising:
(a) preparing a semiconductor substrate having an upper surface;
(b) forming an interlayer insulating film on the upper surface of the semiconductor substrate;
(c) forming a first pad and a second pad having a smaller plane area than a plane area of the first pad on the interlayer insulating film;
(d) forming a seed layer on the first pad and the second pad by a sputtering method;
(e) forming a first plating film on the seed layer on the first pad by an electrolytic plating method;
(f) forming a third plating film on the seed layer on the second pad by an electrolytic plating method; and
(g) forming a fourth plating film on the third plating film by an electrolytic plating method,
wherein a material forming the third plating film differs from a material forming the first plating film,
wherein a material forming the fourth plating film differs from a material forming each of the first plating film and the third plating film,
wherein the material forming the first plating film is a metal other than a noble metal,
wherein the material forming the fourth plating film is a noble metal,
wherein the method further comprises (h) between the (a) and the (b), forming a MOSFET in the semiconductor substrate,
wherein the (c) includes:
(c4) forming a first wiring and a second wiring on the interlayer insulating film;
(c5) forming a first insulating film on the interlayer insulating film to cover the first wiring and the second wiring; and
(c6) forming a first opening in the first insulating film to expose a first portion of the first wiring and forming a second opening in the first insulating film to expose a second portion of the second wiring,
wherein the first pad is the first portion of the first wiring exposed in the first opening,
wherein the second pad is the second portion of the second wiring exposed in the second opening,
wherein the first pad is electrically connected to a source region of the MOSFET, and
wherein the second pad is electrically connected to a drain region of the MOSFET or a gate electrode of the MOSFET.
5 . The method according to claim 4 ,
wherein the material forming the first plating film is copper,
wherein the material forming the third plating film is palladium, and
wherein the material forming the fourth plating film is gold.