Read latency and suspend modes
Methods, systems, and devices for read latency and suspend modes are described. A memory system may operate in a first mode of operation associated with a first set of access operations including executing read operations, executing write operations, and suspending write operations. The memory system may receive, from a host system, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based on limiting a suspension of write operations. For example, the host system may transmit a command including the indication to switch to the second mode of operation. In another example, the host system may write a value to a register at the memory system including the indication to switch to the second mode of operation. Based on receiving the indication from the host system, the memory system may then operate according to the second mode of operation.
1 . A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
operate the memory system in a first mode of operation associated with a decreased latency for executing write operations in accordance with a limit to suspension of write operations performed by the memory system, wherein operating in accordance with the first mode of operation is in response to comparing a quantity of read operations performed during a write suspension duration with a threshold that is stored in a register of the memory system and is associated with the limit to suspension of the write operations;
transmit an indication of a first write execution latency according to the first mode of operation;
receive, in response to transmitting the indication, an indication to switch to a second mode of operation that reduces the limit to suspension of the write operations; and
operate the memory system in accordance with the second mode of operation based at least in part on receiving the indication.
2 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
transmit, prior to operating the memory system in accordance with the first mode of operation, an indication of a second write execution latency of the memory system, wherein the indication to switch to the second mode is received in response to the first write execution latency being less than the second write execution latency.
3 . The memory system of claim 1 , wherein the processing circuitry is configured to cause the memory system to:
receive one or more write commands from a host system prior to operating the memory system in accordance with the first mode of operation, wherein the indication of the first write execution latency comprises an indication that the memory system has completed an execution of the one or more write commands, and wherein the indication to switch to the second mode is received in response to a duration between receiving the one or more write commands and transmitting the indication of the first write execution latency.
4 . The memory system of claim 1 , wherein the processing circuitry is configured to cause the memory system to:
transmit an indication of a capacity of the memory system to receive one or more write commands, to execute one or more write commands, or both, wherein the indication to switch to the second mode is received in response to transmitting the indication of the capacity.
5 . The memory system of claim 1 , wherein the indication to switch to the second mode is received in response to a workload of the memory system comprising a quantity of write operations that satisfies a threshold quantity of write operations.
6 . The memory system of claim 1 , wherein, to receive the indication to switch to the second mode of operation, the processing circuitry is configured to cause the memory system to:
receive a command comprising the indication to switch to the second mode of operation; or
identify that a value of a second register of the memory system comprises the indication to switch to the second mode of operation, the value of the second register being written by a host system.
7 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:
operate a memory system in a first mode of operation associated with a decreased latency for executing write operations in accordance with a limit to suspension of write operations performed by the memory system, wherein operating in accordance with the first mode of operation is in response to comparing a quantity of read operations performed during a write suspension duration with a threshold that is stored in a register of the memory system and is associated with the limit to suspension of the write operations;
transmit an indication of a first write execution latency according to the first mode of operation;
receive, in response to transmitting the indication, an indication to switch to a second mode of operation that reduces the limit to suspension of the write operations; and
operate the memory system in accordance with the second mode of operation based at least in part on receiving the indication.
8 . The non-transitory computer-readable medium of claim 7 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:
transmit, prior to operating the memory system in accordance with the first mode of operation, an indication of a second write execution latency of the memory system, wherein the indication to switch to the second mode is received in response to the first write execution latency being less than the second write execution latency.
9 . The non-transitory computer-readable medium of claim 7 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:
receive one or more write commands from a host system prior to operating the memory system in accordance with the first mode of operation, wherein the indication of the first write execution latency comprises an indication that the memory system has completed an execution of the one or more write commands, and wherein the indication to switch to the second mode is received in response to a duration between receiving the one or more write commands and transmitting the indication of the first write execution latency.
10 . The non-transitory computer-readable medium of claim 7 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:
transmit an indication of a capacity of the memory system to receive one or more write commands, to execute one or more write commands, or both, wherein the indication to switch to the second mode is received in response to transmitting the indication of the capacity.
11 . The non-transitory computer-readable medium of claim 7 , wherein the indication to switch to the second mode is received in response to a workload of the memory system comprising a quantity of write operations that satisfies a threshold quantity of write operations.
12 . The non-transitory computer-readable medium of claim 7 , wherein the instructions to receive the indication to switch to the second mode of operation, when executed by the processing circuitry of the electronic device, further cause the electronic device to:
receive a command comprising the indication to switch to the second mode of operation; or
identify that a value of a second register of the memory system comprises the indication to switch to the second mode of operation, the value of the second register being written by a host system.
13 . A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive an indication to switch to a mode of operation associated with limiting suspending write operations at the memory system;
compare a quantity of read operations performed during a write suspension duration with a threshold associated with limiting the suspending write operations, wherein the threshold is stored in a register at the memory system; and
operate the memory system in accordance with the mode of operation in response to receiving the indication and comparing the quantity of read operations with the threshold.
14 . The memory system of claim 13 , wherein the mode of operation is associated with a set of access operations comprising executing read operations, executing write operations, and executing fewer read operations than the threshold.
15 . The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
select the mode of operation from a plurality of modes of operation configured at the memory system, wherein each of the plurality of modes of operation is associated with a decreased latency for executing write operations in response to limiting the suspending write operations, and wherein operating the memory system in accordance with the mode of operation is in response to the selection.
16 . The memory system of claim 15 , wherein the mode of operation is selected in response to receiving an indication of the mode of operation from a host system, in response to a predicted workload of the memory system, in response to one or more previous operations performed by the memory system, or a combination thereof.
17 . The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
transmit an indication of a write execution latency to a host system, the write execution latency associated with a duration during which the memory system operates in accordance with a second mode of operation that does not limit suspending write operations, wherein the indication to switch to the mode of operation is received from the host system in response to transmitting the indication of the write execution latency.
18 . The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
compare a quantity of write operation suspensions performed during the mode of operation with a second threshold associated with limiting the suspending write operations, wherein operating the memory system in accordance with the mode of operation is further in response to comparing the quantity of write operation suspensions with the second threshold, and wherein the mode of operation is associated with a set of access operations comprising executing read operations, executing write operations, and suspending a quantity of write operations that is less than the threshold.
19 . The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
receive an indication of the threshold from a host system, wherein comparing the quantity of read operations with the threshold is in response to receiving the indication of the threshold.
20 . The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
identify the threshold in response to a predicted workload of the memory system, in response to one or more previous operations performed by the memory system, or both.