Granted Patent B2

US 12,648,135 · App. 18/527,926 · Granted Jun 2, 2026

Inventors: Na Yeong Yang (Gyeonggi-do, KR); Ki Jun Yun (Gyeonggi-do, KR); Jung Shik Jang (Gyeonggi-do, KR); In Su Park (Gyeonggi-do, KR); Seok Min Choi (Gyeonggi-do, KR)

Assignee: SK hynix Inc.

H10B41/30H10B41/23

Abstract

Claims (10)

1 . A semiconductor device comprising:

a first gate structure;

a second gate structure disposed over the first gate structure; and

a channel structure including a first portion extending through the first gate structure, the first portion having a tapered cross section, a second portion having a tapered cross section, and a third portion connecting the first portion with the second portion,

wherein the third portion has a vertical profile, and

wherein the second portion and the third portion extends through the second gate structure.

2 . The semiconductor device of claim 1 , wherein the second portion extends from a top surface of the second gate structure to the third portion which extends from an intermediate level the second gate structure to a bottom surface of the gate structure where it connects with a top surface of the first portion of the channel structure.

3 . The semiconductor device of claim 1 , wherein the first portion has a first width, the second portion has a second width, and the third portion has a third width smaller than the first width or the second width.

4 . The semiconductor device of claim 3 , wherein the third width is smaller than a width of a top surface of the first portion.

5 . The semiconductor device of claim 3 , wherein the third width is substantially the same as a width of a bottom surface of the second portion.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (24)