Trench-type beol memory cell
An integrated chip includes a memory cell within a BEOL metal interconnect. The memory cell may be an FeRAM memory cell. The memory cell is formed over a plurality of openings in a dielectric structure that includes an inter-level dielectric layer. The openings may be form an array or another two-dimensional pattern. The layers of the memory cell line the openings whereby each of a lower electrode layer, a data storage layer, and an upper electrode descend into the openings. The lower electrode layer may pass through an etch stop layer and contact a lower interconnect. There may be a plurality of top electrode vias. The top electrode vias may be offset from the opening. This memory cell structure provides a large area, which leads to low threshold voltages.
1 . A method comprising:
forming a lower interconnect within a lower dielectric structure over a substrate;
forming an etch stop layer over the lower dielectric structure;
forming an inter-level dielectric layer over the etch stop layer;
etching a first opening and a second opening through the inter-level dielectric layer;
forming a memory cell stack over the inter-level dielectric layer and in the first and second openings; and
etching to define a memory cell from the memory cell stack;
wherein an upper electrode of the memory cell descends into each of the first and second openings; and
a lower electrode of the memory cell extends laterally from the first opening to the second opening over the inter-level dielectric layer.
2 . The method of claim 1 , wherein the first and second openings extend through the etch stop layer.
3 . The method of claim 1 , wherein the first and second openings are in a two-dimensional pattern with a third and fourth opening, and the memory cell extends over and in the first, second, third, and fourth openings.
4 . The method of claim 1 , wherein the memory cell is a ferroelectric random access memory cell.
5 . The method of claim 1 , further comprising forming a plurality of top electrode vias each of which contacts the upper electrode.
6 . A method of forming a memory device, the method comprising:
forming a first dielectric structure over a metallization layer of a BEOL interconnect structure disposed on a substrate, the first dielectric structure comprising an inter-level dielectric (ILD) layer;
etching a plurality of openings through the first dielectric structure;
forming a memory cell stack over the plurality of openings, the memory cell stack comprising a lower electrode layer, a data storage layer, and an upper electrode layer, wherein the lower electrode layer and the data storage layer line the plurality of openings, and a portion of the memory cell stack is lateral to the plurality of openings; and
forming a mask that extends over the plurality of openings and etching the memory cell stack to define a memory cell that extends over and into the plurality of openings.
7 . The method of claim 6 , wherein the plurality of openings comprise two or more openings.
8 . The method of claim 6 , wherein the plurality of openings are rectangular.
9 . The method of claim 6 , wherein the plurality of openings are circular.
10 . The method of claim 6 , wherein the plurality of openings are oblong.
11 . The method of claim 6 , further comprising forming a sidewall spacer that surrounds the memory cell, wherein the sidewall spacer contacts the lower electrode layer, data storage layer, and upper electrode layer.
12 . The method of claim 6 , wherein a depth of the plurality of openings is greater than a width of each of the openings.
13 . A method, comprising:
forming a first dielectric structure over a metallization layer in a BEOL interconnect structure disposed over a substrate, the first dielectric structure comprising an inter-level dielectric (ILD) layer and an etch stop layer;
patterning a plurality of openings in the first dielectric structure;
depositing a memory cell stack comprising a lower electrode layer, a data storage layer, and an upper electrode layer such that the lower electrode layer, the data storage layer, and the upper electrode layer extend into the plurality of openings;
patterning the memory cell stack to define a memory cell that extends over and into the plurality of openings; and
forming an upper electrode via that contacts the upper electrode layer.
14 . The method of claim 13 , wherein forming the upper electrode via comprises forming a plurality of upper electrode vias that contact the upper electrode layer.
15 . The method of claim 14 , wherein the upper electrode vias are laterally offset from the openings.
16 . The method of claim 14 , wherein the number of upper electrode vias is distinct from the number of openings.
17 . The method of claim 14 , wherein the lower electrode layer, the data storage layer, and the upper electrode layer are deposited by atomic layer deposition.
18 . The method of claim 14 , wherein the lower electrode layer directly contacts a wire in the metallization layer.
19 . The method of claim 14 , wherein the lower electrode layer contacts a plurality of wires in the metallization layer.
20 . The method of claim 14 , wherein the plurality of openings extend into the etch stop layer beneath the ILD layer.