Fabrication of gate-all-around integrated circuit structures having additive gate structures
Gate-all-around integrated circuit structures having additive gate structures are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the P-type conductive layer and the first gate dielectric. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the N-type conductive layer and the second gate dielectric. The P-type gate stack is in contact with the N-type gate stack.
1 . An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a P-type gate stack over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the P-type conductive layer and the first gate dielectric; and
an N-type gate stack over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the N-type conductive layer and the second gate dielectric, wherein the P-type gate stack is in contact with the N-type gate stack, and wherein the intervening conductive seed layer comprises molybdenum and silicon, or the intervening conductive seed layer comprises tungsten and silicon.
2 . The integrated circuit structure of claim 1 , wherein the intervening conductive seed layer comprises the molybdenum and silicon.
3 . The integrated circuit structure of claim 1 , wherein the intervening conductive seed layer has a thickness of 1 nanometer or less.
4 . The integrated circuit structure of claim 1 , wherein the intervening conductive seed layer comprises the tungsten and silicon.
5 . The integrated circuit structure of claim 1 , wherein one or both of the P-type gate stack or the N-type gate stack includes a dipole layer.
6 . An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first P-type gate stack over the first vertical arrangement of horizontal nanowires, the first P-type gate stack having a first P-type conductive layer over a first gate dielectric, and the intervening conductive seed layer between the first P-type conductive layer and the first gate dielectric; and
a second P-type gate stack over the second vertical arrangement of horizontal nanowires, the second P-type gate stack having a second P-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the second P-type conductive layer and the second gate dielectric, wherein the second P-type gate stack is different than the first P-type gate stack, wherein the first P-type gate stack is in contact with the second P-type gate stack, and wherein the intervening conductive seed layer comprises molybdenum and silicon, or the intervening conductive seed layer comprises tungsten and silicon.
7 . The integrated circuit structure of claim 6 , wherein the intervening conductive seed layer comprises the molybdenum and silicon.
8 . The integrated circuit structure of claim 6 , wherein the intervening conductive seed layer has a thickness of 1 nanometer or less.
9 . The integrated circuit structure of claim 6 , wherein the intervening conductive seed layer comprises the tungsten and silicon.
10 . The integrated circuit structure of claim 6 , wherein one or both of the first P-type gate stack or the second P-type gate stack includes a dipole layer.
11 . An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first N-type gate stack over the first vertical arrangement of horizontal nanowires, the first N-type gate stack having a first N-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the first N-type conductive layer and the first gate dielectric; and
a second N-type gate stack over the second vertical arrangement of horizontal nanowires, the second N-type gate stack having a second N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the second N-type conductive layer and the second gate dielectric, wherein the second N-type gate stack is different than the first N-type gate stack, wherein the first N-type gate stack is in contact with the second N-type gate stack, and wherein the intervening conductive seed layer comprises molybdenum and silicon, or the intervening conductive seed layer comprises tungsten and silicon.
12 . The integrated circuit structure of claim 11 , wherein the intervening conductive seed layer comprises the molybdenum and silicon.
13 . The integrated circuit structure of claim 12 , wherein the intervening conductive seed layer has a thickness of 1 nanometer or less.
14 . The integrated circuit structure of claim 11 , wherein the intervening conductive seed layer comprises the tungsten and silicon.
15 . The integrated circuit structure of claim 11 , wherein one or both of the first N-type gate stack or the second N-type gate stack includes a dipole layer.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a P-type gate stack over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the P-type conductive layer and the first gate dielectric; and
an N-type gate stack over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the N-type conductive layer and the second gate dielectric, wherein the P-type gate stack is in contact with the N-type gate stack, and wherein the intervening conductive seed layer comprises molybdenum and silicon, or the intervening conductive seed layer comprises tungsten and silicon.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 17 , wherein the component is a packaged integrated circuit die.
19 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
20 . The computing device of claim 16 , further comprising:
a battery coupled to the board.