Semiconductor device and method
Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.
1 . A method for forming a semiconductor device, the method comprising:
providing a substrate;
forming on the substrate a plurality of fins and a dielectric fin formed of dielectric material;
forming a dummy gate structure over the plurality of fins and over the dielectric fin;
depositing a hard mask over the dummy gate structure;
etching an opening through the hard mask to expose the dummy gate structure;
depositing a conformal layer over the hard mask and within the opening;
etching the conformal layer to form spacers within the opening;
extending the opening through the dummy gate structure to form a recess, the recess exposing the dielectric fin; and
forming a gate isolation structure contacting the dielectric fin within the recess.
2 . The method of claim 1 , wherein the conformal layer is formed of a material selected from the group consisting of a nitride, an oxide, and a metal oxide.
3 . The method of claim 1 , wherein the step of forming the dielectric fin comprises removing one fin of the plurality of fins and depositing the dielectric fin in a recess formed during the step of removing the one fin of the plurality of fins.
4 . The method of claim 1 , wherein the step of depositing the conformal layer releases a stress in the underlying structure.
5 . The method of claim 1 , wherein the conformal layer comprises a silicon oxide sublayer and a silicon nitride sublayer on the silicon oxide sublayer.
6 . The method of claim 1 , wherein the step of depositing the conformal layer includes first depositing a stress-relieving sub-layer and then depositing on the stress-relieving sub-layer a second sub-layer that increases the density of the conformal layer.
7 . The method of claim 1 , further comprising etching regions of the conformal layer to form a liner lining sidewalls of the opening.
8 . The method of claim 7 , wherein the liner has a shape of a closed polygon when viewed from a plan view.
9 . The method of claim 8 , wherein the liner has a shape of a closed curve when viewed from a plan view.
10 . A method for forming a semiconductor device, the method comprising:
providing a substrate;
forming a plurality of channel regions over the substrate and forming a dummy fin interjacent two channel regions of the plurality of channel regions;
forming a dummy gate structure over the plurality of channel regions and over the dummy fin;
depositing a hard mask over the dummy gate structure;
etching an opening through the hard mask to expose the dummy gate structure, the opening being aligned to the dummy fin;
depositing a conformal layer over the hard mask and within the opening to define a narrower opening;
etching the conformal layer to form spacers within the narrower opening;
etching through the narrower opening to form a recess within the dummy gate structure; and
forming a gate isolation structure within the recess, the gate isolation structure contacting the dummy fin.
11 . The method of claim 10 , wherein at least one of the channel regions is defined within a semiconductor fin extending from the substrate.
12 . The method of claim 11 , wherein at least one of the channel regions is located within a stack of channel regions and the dummy gate structure surrounds respective ones of the stack of channel regions.
13 . The method of claim 10 , wherein the step of forming the gate isolation structure within the recess includes depositing a material selected from the group consisting of one or more layers of silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, and combinations thereof, using a deposition process selected from ALD, PEALD, and thermal ALD.
14 . The method of claim 10 , further comprising:
removing the dummy gate structure; and
forming a metal gate structure in place of the removed dummy gate structure.
15 . The method of claim 10 , wherein the conformal layer is deposited to a thickness in the range of 3 nm to 5 nm.
16 . A method for forming a semiconductor device, the method comprising:
forming at least one first channel region in a first fin, at least one second channel region in a second fin, a dummy fin structure interjacent the at least one first channel region and the at least one second channel region, and a dummy gate structure extending continuously over the at least one first channel region, the at least one second channel region, and the dummy fin structure;
depositing a masking layer over the dummy gate structure;
forming a first opening in the masking layer, the first opening being aligned to the dummy fin structure, the first opening exposing a top surface of the dummy gate structure, the first opening having a first width, in a cross-sectional view;
lining the first opening with a spacer layer to form a lined opening, the lined opening having a second width, in the cross-section view, the second width being less than the first width;
after forming the lined opening, etching the dummy gate structure through the lined opening to form a third opening, the third opening exposing the dummy fin structure; and
filling the third opening with a dielectric material, wherein the dummy fin structure and the dielectric material form a gate isolation structure that electrically insulates a subsequently-formed first active gate structure from a subsequently-formed second active gate structure.
17 . The method of claim 16 , wherein the dummy fin structure comprises a dielectric fin structure deposited in a recess formed by removing a dummy semiconductor fin.
18 . The method of claim 16 , wherein the step of lining the first opening with the spacer layer to form the lined opening includes:
conformally depositing a liner material on the masking layer and on sidewalls of the first opening and on a portion of the dummy gate structure exposed by the first opening; and
etching back the liner material on the masking layer and on the portion of the dummy gate structure exposed by the first opening, while leaving the liner material on sidewalls of the first opening.
19 . The method of claim 16 , wherein the including at least one first channel region comprises a vertical stack of channel regions, and further wherein the dummy gate structure surrounds individual ones of the vertical stack of channel regions.
20 . The method of claim 16 , further comprising:
removing the dummy gate structure;
forming the subsequently-formed first active gate structure over the at least one first channel region; and
forming the subsequently-formed second active gate structure over the at least one second channel region, wherein the first active gate structure and the second active gate structure are physically separated by the dummy fin structure and the dielectric material.