Semiconductor integrated circuit device including an electrostatic discharge protection circuit
A semiconductor integrated circuit device may include a first region, a second region, a pad structure and an electrostatic discharge (ESD) connection. The first region may be positioned adjacent to a semiconductor substrate. An ESD protection circuit may be integrated in the first region. The second region may be stacked on the first region. A plurality of memory cells may be formed in the second region. The pad structure may be arranged over the second region to receive an external voltage. The ESD connection may include a plurality of lower conductive wirings in the first region. At least one of the lower conductive wirings may be electrically connected with the ESD protection circuit. The at least one of the lower conductive wirings may be drawn to a portion corresponding to the pad structure.
1 . A semiconductor integrated circuit device comprising:
a first region, arranged adjacent to a semiconductor substrate, that includes an electrostatic discharge (ESD) protection circuit;
a second region, stacked on the first region in a vertical direction, that includes a plurality of memory cells;
a pad structure, arranged over the second region, that receives an external voltage; and
an ESD connection configured to connect the ESD protection circuit and the pad structure,
wherein, in a plan view, a portion of the ESD connection facing the pad structure is configured in a mesh shape.
2 . The semiconductor integrated circuit device of claim 1 , wherein the ESD connection comprises:
a first lower conductive wiring disposed over the ESD protection circuit;
a second lower conductive wiring disposed over the first lower conductive wiring; and
a third lower conductive wiring extending toward the pad structure to face the pad structure and electrically connecting to the second lower conductive wiring, and
wherein the first to third lower conductive wirings are sequentially stacked on the ESD protection circuit.
3 . The semiconductor integrated circuit device of claim 2 , wherein the ESD protection circuit comprises a diode region including an anode region and a cathode region, and
wherein at least one of the anode region and the cathode region is electrically connected to the ESD connection.
4 . The semiconductor integrated circuit device of claim 2 , wherein the third lower conductive wiring facing to the pad structure has the mesh shape, and the third lower conductive wiring having the mesh shape comprises a plurality of perpendicular patterns that intersect with a plurality of horizontal patterns that are coplanar.
5 . The semiconductor integrated circuit device of claim 1 , wherein the pad structure comprises a pad and at least one upper conductive wiring connecting the pad and the ESD connection.
6 . The semiconductor integrated circuit device of claim 5 , further comprising a revision disposed between the pad and the upper conductive wiring to selectively connect or disconnect the pad with or from the upper conductive wiring.
7 . The semiconductor integrated circuit device of claim 5 , further comprising a plurality of power lines coplanar with the pad structure and arranged over the ESD protection circuit.
8 . The semiconductor integrated circuit device of claim 5 , wherein the second region further comprises a plurality of source lines, a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells,
wherein the at least one upper conductive wiring includes a first upper conductive wiring disposed coplanar with the bit lines, and
wherein the ESD connection has a thickness greater than thicknesses of the bit lines and the first upper conductive wiring.
9 . The semiconductor integrated circuit device of claim 1 , further comprising a buried contact extending through the second region and partially through the first region.
10 . A semiconductor integrated circuit device:
a cell region including a plurality of memory cells, upper conductive wirings electrically connected with the memory cells, a pad structure configured to receive an external signal and disposed over the cell region, and at least one power line configured to transmit a voltage;
a peripheral circuit region disposed under the cell region, the peripheral circuit region including an ESD protection circuit arranged between the cell region and a semiconductor substrate to discharge a static electricity inputted through the pad structure,
wherein the ESD protection circuit comprises:
a plurality of protection element regions including a first electrode region and a second electrode region isolated from the first electrode region;
at least one lower conductive wiring electrically connected to the first electrode region and the second electrode region; and
an uppermost lower conductive wiring arranged on the least one lower conductive wiring, the uppermost lower conductive wiring including a first electrode correspondence corresponding to the first electrode region, a second electrode correspondence corresponding to the second electrode region, and an ESD connection arranged therebetween and configured to electrically connect the lower conductive wiring to the pad structure.
11 . The semiconductor integrated circuit device of claim 10 , wherein the first electrode region comprises a cathode region electrically connected to the least one power line and the second electrode region comprises an anode region electrically connected to the pad structure when a driving voltage is applied to the least one power line, and
the first electrode region comprises an anode region electrically connected to the least one power line and the second electrode region comprises a cathode region electrically connected to the pad structure when a ground voltage is applied to the least one power line.
12 . The semiconductor integrated circuit device of claim 10 , wherein the uppermost lower conductive wiring has a thickness greater than thicknesses of the upper conductive wirings, and the first electrode region has a frame-shape and the second electrode region has a patterned shape.
13 . The semiconductor integrated circuit device of claim 10 , wherein the uppermost lower conductive wiring facing the pad structure has a mesh shape including coplanar horizontal patterns and vertical patterns.
14 . The semiconductor integrated circuit device of claim 10 , wherein the first electrode correspondence is positioned over the first electrode region parallel to the second electrode region and the first electrode correspondence is spaced apart from the ESD connection.
15 . The semiconductor integrated circuit device of claim 10 , wherein the upper conductive wirings comprise:
a bit line electrically connected to the memory cells;
an electrode wiring arranged to correspond to the first electrode correspondence; and
a connection wiring arranged to correspond to the ESD connection.
16 . The semiconductor integrated circuit device of claim 15 , wherein the cell region further comprises:
a buried insulation layer disposed on the memory cells, the buried insulation layer having a total thickness greater than a height of the memory cells; and
a buried contact configured to electrically connect the first electrode correspondence with the electrode wiring and to electrically connect the ESD connection with the connection wiring.
17 . The semiconductor integrated circuit device of claim 15 , wherein the pad structure is arranged on the cell region with the upper conductive wirings, and the pad structure comprises a pad configured to receive the external signal and a pad connection arranged adjacent to the pad to overlap with the connection wiring and to electrically connect to the connection wiring.
18 . The semiconductor integrated circuit device of claim 17 , further comprising a revision configured to selectively connect the pad with the pad connection.
19 . The semiconductor integrated circuit device of claim 10 , wherein the plurality of protection element regions and the pad structure are electrically connected through the at least one lower conductive wiring, the uppermost lower conductive wring and the upper conductive wirings.