Display panel and display apparatus
A display panel and a display apparatus. The display panel includes: a substrate including a first non-display area and a display area arranged around the first non-display area; and a plurality of pixel circuits arranged in a plurality of rows in the display area, each row of the pixel circuits includes a plurality of pixel circuits arranged in the first direction, the plurality of rows of the pixel circuits are arranged in the second direction, the second direction intersects the first direction, each of the pixel circuits includes a semiconductor layer for forming an active layer of a transistor, in which the semiconductor layers of adjacent ones of the pixel circuits are spaced apart from each other.
1 . A display panel, comprising:
a substrate comprising a first non-display area and a display area arranged around the first non-display area;
a plurality of pixel circuits arranged in a plurality of rows extending along a first direction and a plurality of columns extending along a second direction in the display area, the first direction and the second direction intersecting each other, and each of the pixel circuits comprising a semiconductor layer for forming an active layer of a transistor, wherein the semiconductor layers of adjacent ones of the pixel circuits in the second direction are spaced apart from each other;
a plurality of light-emitting elements arranged in the display area, each of the light-emitting elements comprising a first electrode, an organic light-emitting layer, and a second electrode; and
a plurality of scan lines extending along the first direction;
wherein each of the pixel circuits comprises a driving transistor, a first resetting transistor and a second resetting transistor, the driving transistor is electrically connected to a corresponding light-emitting element to provide a drive current to the light-emitting element, the first resetting transistor is electrically connected to a gate of the driving transistor to reset the gate of the driving transistor, and the second resetting transistor is electrically connected to the first electrode of the light-emitting element to reset the first electrode;
the semiconductor layer of each of the pixel circuits comprises an active layer of the driving transistor, a first active layer of the first resetting transistor and a second active layer of the second resetting transistor, wherein,
in the same pixel circuit, the first active layer of the first resetting transistor and the second active layer of the second resetting transistor are located on opposite sides of the driving transistor along the second direction, the active layer of the driving transistor is connected to a first terminal of the second active layer of the second resetting transistor, and the active layer of the driving transistor is connected to a first terminal of the first active layer of the first resetting transistor,
in two pixel circuits adjacent along the second direction, the first active layer of the first resetting transistor in one pixel circuit and the second active layer of the second resetting transistor in the other pixel circuit are spaced apart from each other and arranged along the first direction, a second terminal of the first active layer of the first resetting transistor in one pixel circuit and a second terminal of the second active layer of the second resetting transistor in the other pixel circuit are spaced apart from each other and arranged along the first direction to form a gap.
2 . The display panel of claim 1 , further comprising:
a plurality of preset signal lines extending along the first direction, each of the preset signal lines being electrically connected to the semiconductor layers of corresponding adjacent two rows of the pixel circuits to simultaneously provide a preset signal to the adjacent two rows of the pixel circuits.
3 . The display panel of claim 2 , wherein in the adjacent two rows of the pixel circuits electrically connected to the preset signal line, the semiconductor layers of one of the adjacent two rows of the pixel circuits comprise a first node to which the preset signal line is electrically connected, the semiconductor layers of the other of the adjacent two rows of the pixel circuits comprise a second node to which the preset signal line is electrically connected, and the semiconductor layers of adjacent ones of the pixel circuits are spaced apart from each other between the first node and the second node.
4 . The display panel of claim 1 , further comprising:
a plurality of preset signal lines extending along the first direction, wherein the preset signal lines are reference voltage lines configured to provide a reference voltage signal for resetting a preset node of the pixel circuits.
5 . The display panel of claim 1 , wherein
the first electrode being located at a side of the organic light-emitting layer facing the substrate, the second electrode being located at a side of the organic light-emitting layer away from the substrate, and the first electrode of each of the light-emitting elements being electrically connected to a corresponding one of the pixel circuits, and the light-emitting element further comprises at least one of a hole injection layer, a hole transporting layer, an electron injection layer or an electron transporting layer arranged between the first electrode and the second electrode.
6 . The display panel of claim 4 , wherein each of the preset signal lines extends between corresponding adjacent two rows of the pixel circuits, each of the preset signal lines is electrically connected to the first active layers of one of the adjacent two rows of the pixel circuits and is electrically connected to the second active layers of the other of the adjacent two rows of the pixel circuits.
7 . The display panel of claim 4 , further comprising:
interconnecting structures for electrically connecting the preset signal lines to the semiconductor layers of corresponding adjacent two rows of the pixel circuits, the interconnecting structures being located in a different layer from the semiconductor layers, and the interconnecting structures and the semiconductor layers being connected through vias.
8 . The display panel of claim 7 , wherein the display panel comprises a plurality of conductive layers and a plurality of insulating layers arranged on the substrate, wherein the interconnecting structures are arranged in the conductive layers located at a side of the preset signal lines away from the substrate, and the interconnecting structures and the preset signal lines are connected through vias.
9 . The display panel of claim 7 , wherein the interconnecting structures are interconnecting blocks, each of the interconnecting blocks is connected to the semiconductor layers of corresponding adjacent two of the pixel circuits in the second direction through a first via and a second via, and each of the interconnecting blocks is connected to a corresponding preset signal line through a third via.
10 . The display panel of claim 7 , wherein each of the interconnecting structures comprises a first sub-interconnecting block and a second sub-interconnecting block spaced apart from each other, the first sub-interconnecting block and the second sub-interconnecting block electrically connect the semiconductor layers of corresponding adjacent two of the pixel circuits in the second direction to a corresponding preset signal line, wherein the first sub-interconnecting block is connected to the semiconductor layer of one of the adjacent two of the pixel circuits through a fourth via, the second sub-interconnecting block is connected to the semiconductor layer of the other of the adjacent two of the pixel circuits through a fifth via, the first sub-interconnecting block is connected to the preset signal line through a sixth via, and the second sub-interconnecting block is connected to the preset signal line through a seventh via.
11 . The display panel of claim 5 , further comprising:
an encapsulation layer covering the plurality of light-emitting elements; and
a cover plate layer located at a side of the encapsulation layer away from the substrate, wherein the display area comprises a first boundary and a second boundary opposite to each other in the second direction, and a spacing between the first non-display area and the first boundary is not equal to a spacing between the first non-display area and the second boundary.
12 . The display panel of claim 1 , wherein the semiconductor layer is a silicon semiconductor layer or an oxide semiconductor layer.
13 . A display apparatus comprising the display panel of claim 1 , wherein the first non-display area is configured as a light-transmitting area.
14 . The display apparatus of claim 13 , wherein the display panel comprises a display surface and a non-display surface opposite to each other, the display apparatus further comprises:
a photosensitive component, located at a side of the display panel where the non-display surface is located, and arranged correspondingly to the first non-display area of the display panel, wherein the photosensitive component comprises at least one of an image capturing component, an infrared sensor, or a proximity sensor.
15 . The display panel of claim 1 , wherein in the two pixel circuits adjacent along the second direction, the first active layer of the first resetting transistor in one pixel circuit and located on a side of the one pixel circuit close to the other pixel circuit, and the second active layer of the second resetting transistor in the other pixel circuit and located on a side of the other pixel circuit close to the one pixel circuit, are spaced apart from each other, the second terminal of the first active layer of the first resetting transistor in the one pixel circuit and located on the side of the one pixel circuit close to the other pixel circuit, and the second terminal of the second active layer of the second resetting transistor in the other pixel circuit and located on the side of the other pixel circuit close to the one pixel circuit, are spaced apart from each other and arranged along the first direction to form the gap.
16 . The display panel of claim 1 , wherein, in the two pixel circuits adjacent along the second direction, a projection of the first active layer of the first resetting transistor in one pixel circuit on the substrate and a projection of the second active layer of the second resetting transistor in the other pixel circuit on the substrate are spaced apart from each other, and overlap with a projection of the same scan line on the substrate.
17 . The display panel of claim 1 , wherein the semiconductor layers of adjacent ones of the pixel circuits in the first direction are spaced apart from each other.
18 . The display panel of claim 1 , further comprising:
a plurality of light-emitting control lines extending along the first direction, wherein each of the pixel circuits further comprises a third transistor,
the semiconductor layer of each of the pixel circuits further comprises an active layer of the third transistor;
in the same pixel circuit, the active layer of the driving transistor is connected to the first terminal of the second active layer of the second resetting transistor by the active layer of the third transistor,
a projection of the active layer of the third transistor on the substrate overlaps with a projection of the light-emitting control line on the substrate.
19 . The display panel of claim 18 , wherein each pixel circuit further comprises a fourth transistor, and the semiconductor layer of each pixel circuit further comprises an active layer of the fourth transistor;
in the same pixel circuit, the active layer of the driving transistor is connected to the first terminal of the first active layer of the first resetting transistor by the active layer of the fourth transistor.
20 . The display panel of claim 1 , wherein the plurality of scan lines comprises a plurality of first scan lines extending along the first direction,
in the two pixel circuits adjacent along the second direction, a projection of the first active layer of the first resetting transistor in one pixel circuit on the substrate and a projection of the second active layer of the second resetting transistor in the other pixel circuit on the substrate overlap with a projection of a same first scan line on the substrate; projections of the second terminal of the first active layer of the first resetting transistor in one pixel circuit and the second terminal of the second active layer of the second resetting transistor in the other pixel circuit on the substrate are located on the same side of the projection of the same first scan line on the substrate, and spaced apart from each other and arranged along the first direction to form the gap; projections of the first terminal and the second terminal of the second active layer of the second resetting transistor in the other pixel circuit on the substrate are located on opposite sides of the projection of the same first scan line on the substrate.