IP Library › Granted Patent US 12,648,497
Granted Patent B2
US 12,648,497 · App. 18/215,830 · Granted Jun 2, 2026

Semiconductor package using substrate block integration

Inventors: Wei-Chih Chen (Hsinchu City, TW); Shi-Bai Chen (Hsinchu City, TW)
Assignee: MEDIATEK INC.
H10W90/401H10B80/00H10W90/00H10W72/252H10W74/15H10W90/724H10W90/734
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,648,497
App. No.
18/215,830
Granted
Jun 2, 2026
Kind
B2
Abstract

A semiconductor package includes a partitioned package substrate composed of substrate parts arranged in a side-by-side manner; an integrated circuit die mounted on a first surface of the partitioned package substrate; and solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface.

Claims (31)

1 . A semiconductor package, comprising:

a partitioned package substrate composed of a plurality of substrate parts arranged in a side-by-side manner, wherein the plurality of substrate parts are rearranged and adjoined together with a gap therebetween, and wherein the plurality of substrate parts are adjoined together by using an adhesive that fills into the gap;

at least one integrated circuit die mounted on a first surface of the partitioned package substrate; and

a plurality of solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface.

2 . The semiconductor package according to claim 1 , wherein the at least one integrated circuit die is electrically connected to the partitioned package substrate through a plurality of conductive elements.

3 . The semiconductor package according to claim 2 , wherein the conductive elements comprise micro-bumps, copper bumps or copper pillars.

4 . The semiconductor package according to claim 1 , wherein the plurality of substrate parts are physically separated from one another.

5 . The semiconductor package according to claim 1 , wherein the gap has a width ranging between 1-3 mm.

6 . The semiconductor package according to claim 1 , wherein the plurality of substrate parts are homogeneous substrates.

7 . The semiconductor package according to claim 1 , wherein the plurality of substrate parts are heterogeneous substrates.

8 . The semiconductor package according to claim 1 , wherein the plurality of substrate parts have the same thickness.

9 . The semiconductor package according to claim 1 , wherein the plurality of substrate parts have different thicknesses.

10 . The semiconductor package according to claim 1 further comprising:

at least one die mounted on the first surface of the partitioned package substrate in a flip-chip manner.

11 . The semiconductor package according to claim 10 , wherein the at least one die is a dummy die.

12 . The semiconductor package according to claim 10 , wherein the at least one die is a memory die.

13 . The semiconductor package according to claim 1 further comprising:

a second integrated circuit die; and

an electronic device mounted on the first surface of the partitioned package substrate.

14 . The semiconductor package according to claim 13 , wherein the electronic device comprises a decoupling capacitor.

15 . The semiconductor package according to claim 13 , wherein the second integrated circuit die and the electronic device do not overlap with the gap.

16 . The semiconductor package according to claim 1 further comprising:

an annular frame mounted on the first surface of the partitioned package substrate.

17 . The semiconductor package according to claim 16 , wherein the frame is a metal frame.

18 . The semiconductor package according to claim 16 , wherein the frame is attached to the first surface of the partitioned package substrate by using joint bumps.

19 . The semiconductor package according to claim 16 , wherein the frame is attached to the first surface of the partitioned package substrate by using adhesive.

20 . The semiconductor package according to claim 16 , wherein the frame comprise an opening for accommodating the at least one integrated circuit die.

21 . The semiconductor package according to claim 1 further comprising:

a lid installed on the first surface of the partitioned package substrate, wherein the at least one integrated circuit die is housed by the lid and encapsulated by a mold cap.

22 . The semiconductor package according to claim 1 further comprising:

a re-distribution layer (RDL) structure on the first surface of the partitioned package substrate, wherein the at least one integrated circuit die is mounted on the RDL structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2023
From: CHEN, WEI-CHIH; CHEN, SHI-BAI
To: MEDIATEK INC.
Reel/Frame 064106/0732 →
Continuity (2)
Provisional Application 63369980 · Aug 1, 2022
Related Publication 20240038647A1 · Feb 1, 2024
References Cited (6)
US 8704364B2 · Banijamali · 2014 [cited by examiner]
US 20200312826A1 · Jung · 2020 [cited by applicant]
US 20210111141A1 · Sauter · 2021 [cited by examiner]
US 20210143119A1 · Huang · 2021 [cited by applicant]
US 20210175163A1 · Fang · 2021 [cited by applicant]
US 20210265290A1 · Liu · 2021 [cited by applicant]