Mixed signal circuitry for bitwise multiplication with different accuracies
An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform, with a first accuracy, a first portion of a bitwise multiplication of first and second digital inputs and to perform, with a second accuracy different than the first accuracy, at least a second portion of the bitwise multiplication.
1 . An apparatus comprising:
multiply-accumulate circuitry, the multiply-accumulate circuitry comprising a set of two or more instances of bitwise dot-product summation circuitry, a first subset of the set of two or more instances of the bitwise dot-product summation circuitry utilizing first analog hardware and a second subset of the set of two or more instances of the bitwise dot-product summation circuitry utilizing second analog hardware, the second analog hardware being different than the first analog hardware;
at least one processor; and
at least one memory including instruction code;
the at least one memory and the instruction code being configured to, with the at least one processor, cause the apparatus at least to:
perform, with a first accuracy, a first portion of a bitwise multiplication of first and second digital inputs using the first analog hardware; and
perform, with a second accuracy different than the first accuracy, at least a second portion of the bitwise multiplication of the first and second digital inputs using the second analog hardware;
wherein the first analog hardware comprises two or more pop-counter circuit instances each configured to sum a first number of inputs utilizing a bit-design of a first number of bits; and
wherein the second analog hardware comprises a single pop-counter circuit instance coupled to an additional capacitor bank configured to sum a second number of inputs utilizing the bit-design of the first number of bits, the second number of inputs being greater than the first number of inputs.
2 . The apparatus of claim 1 , wherein the bitwise multiplication of the first and second digital inputs comprises computation of a set of weighted sums of bitwise dot products of the first and second digital inputs, wherein the first portion of the bitwise multiplication of the first and second digital inputs comprises a first subset of the set of weighted sums of the bitwise dot products of the first and second digital inputs, and wherein the second portion of the bitwise multiplication of the first and second digital inputs comprises a second subset of the set of weighted sums of the bitwise dot products of the first and second digital inputs.
3 . The apparatus of claim 2 , wherein the set of weighted sums of the bitwise dot products of the first and second digital inputs comprises n weighted sums of the bitwise dot products of the first and second digital inputs, wherein the first portion of the bitwise multiplication performed with the first accuracy comprises computation of the k highest weighted sums of the bitwise dot products of the first and second digital inputs, and wherein the second portion of the bitwise multiplication performed with the second accuracy comprises computation of at least a portion of a remaining n−k weighted sums of the bitwise dot products of the first and second digital inputs.
4 . The apparatus of claim 3 , wherein a value of k is selected based at least in part on determining additive noise contributions of different terms of the bitwise multiplication of the first and second digital inputs.
5 . The apparatus of claim 1 , wherein each of the two or more pop-counter circuit instances of the first analog hardware has a first resolution and the single pop-counter circuit instance of the second analog hardware has a second resolution different than the first resolution.
6 . The apparatus of claim 1 , wherein each of the two or more pop-counter circuit instances of the first analog hardware comprises a successive approximation register analog-to-digital converter comprising a first type of comparator, wherein the single pop-counter circuit instance of the second analog hardware comprises a successive approximation register analog-to-digital converter comprising a second type of comparator, wherein the first type of comparator is different than the second type of comparator.
7 . The apparatus of claim 6 , wherein at least one of:
the first type of comparator has a first noise profile and the second type of comparator has a second noise profile different than the first noise profile; and
the first type of comparator has a first offset cancellation accuracy and the second type of comparator has a second offset cancellation accuracy different than the first offset cancellation accuracy.
8 . The apparatus of claim 1 , wherein each of the two or more pop-counter circuit instances of the first analog hardware comprises a successive approximation register analog-to-digital converter comprising a first plurality of capacitors having respective first sizes, and wherein the single pop-counter circuit instance of the second analog hardware comprises a successive approximation register analog-to-digital converter comprises a second plurality of capacitors having respective second sizes different than the first sizes.
9 . The apparatus of claim 1 , wherein the first analog hardware comprises a first number of charge-sharing capacitors and the second analog hardware comprises a second number of charge-sharing capacitors, the second number of charge-sharing capacitors being different than the first number of charge-sharing capacitors.
10 . The apparatus of claim 1 , wherein the first analog hardware comprises a first set of charge-sharing capacitors with a first size and the second analog hardware comprises a second set of charge-sharing capacitors with a second size, the second size being different than the first size.
11 . The apparatus of claim 1 , wherein the first analog hardware comprises a first comparator with a first noise profile and the second analog hardware comprises a second comparator with a second noise profile, the second noise profile being different than the first noise profile.
12 . The apparatus of claim 1 , wherein the first analog hardware comprises a first comparator with a first offset cancellation and the second analog hardware comprises a second comparator with a second offset cancellation, the second offset cancellation being different than the first offset cancellation.
13 . The apparatus of claim 1 wherein the single pop-counter circuit instance of the second analog hardware is coupled to the additional capacitor bank via a switch, the switch being closed in a first mode of operation for a summation operating phase and being open in a second mode of operation for a successive approximation register phase.
14 . A method, comprising the steps of:
performing, with a first accuracy, a first portion of a bitwise multiplication of first and second digital inputs using a first subset of a set of two or more instances of bitwise dot-product summation circuitry, the first subset of the set of two or more instance of the bitwise dot-product summation circuitry utilizing first analog hardware; and
performing, with a second accuracy different than the first accuracy, at least a second portion of the bitwise multiplication of the first and second digital inputs using a second subset of the set of two or more instances of the bitwise dot-product summation circuitry, the second subset of the set of two or more instances of the bitwise dot-product summation circuitry utilizing second analog hardware, the second analog hardware being different than the first analog hardware;
wherein the method is executed by processing circuitry configured to execute instruction code;
wherein the first analog hardware comprises two or more pop-counter circuit instances each configured to sum a first number of inputs utilizing a bit-design of a first number of bits; and
wherein the second analog hardware comprises a single pop-counter circuit instance coupled to an additional capacitor bank configured to sum a second number of inputs utilizing the bit-design of the first number of bits, the second number of inputs being greater than the first number of inputs.
15 . The method of claim 14 , wherein the bitwise multiplication of the first and second digital inputs comprises computation of a set of weighted sums of bitwise dot products of the first and second digital inputs, wherein the first portion of the bitwise multiplication of the first and second digital inputs comprises a first subset of the set of weighted sums of the bitwise dot products of the first and second digital inputs, and wherein the second portion of the bitwise multiplication of the first and second digital inputs comprises a second subset of the set of weighted sums of the bitwise dot products of the first and second digital inputs.
16 . An article of manufacture comprising a non-transitory computer-readable storage medium having embodied therein executable instruction code that when executed by a processor causes the processor to perform the steps of:
performing, with a first accuracy, a first portion of a bitwise multiplication of first and second digital inputs using a first subset of a set of two or more instances of bitwise dot-product summation circuitry, the first subset of the set of two or more instance of the bitwise dot-product summation circuitry utilizing first analog hardware; and
performing, with a second accuracy different than the first accuracy, at least a second portion of the bitwise multiplication of the first and second digital inputs using a second subset of the set of two or more instances of the bitwise dot-product summation circuitry, the second subset of the set of two or more instances of the bitwise dot-product summation circuitry utilizing second analog hardware, the second analog hardware being different than the first analog hardware;
wherein the first analog hardware comprises two or more pop-counter circuit instances each configured to sum a first number of inputs utilizing a bit-design of a first number of bits; and
wherein the second analog hardware comprises a single pop-counter circuit instance coupled to an additional capacitor bank configured to sum a second number of inputs utilizing the bit-design of the first number of bits, the second number of inputs being greater than the first number of inputs.
17 . The article of claim 16 , wherein the bitwise multiplication of the first and second digital inputs comprises computation of a set of weighted sums of bitwise dot products of the first and second digital inputs, wherein the first portion of the bitwise multiplication of the first and second digital inputs comprises a first subset of the set of weighted sums of the bitwise dot products of the first and second digital inputs, and wherein the second portion of the bitwise multiplication of the first and second digital inputs comprises a second subset of the set of weighted sums of the bitwise dot products of the first and second digital inputs.