Power management of display data during an idle screen
An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple functional blocks. When control circuitry detects a low-performance mode, commands are sent to the multiple functional blocks specifying storing data of the given type in a contiguous manner in one or more of the caches of the multiple functional blocks and the memories connected to the multiple functional blocks. Following, the control circuitry transitions the memories to a sleep state and transitions all but one of the functional blocks to the sleep state. The functional blocks rotate amongst themselves with a single functional block being in the active state and servicing requests based on which data of the given type is targeted by the requests.
1 . An integrated circuit comprising:
a plurality of functional blocks configured to store data in an interleaved manner;
and control circuitry;
wherein responsive to a mode of operation, the control circuitry is configured to:
cause data that is stored in two or more of the plurality of functional blocks to be transferred to a selected block of the functional blocks such that the data is stored
within the selected block in a contiguous manner; and
selectively activate one or more of the plurality of functional blocks to service memory requests based on servicing requirements, while placing at least one other
functional block in a reduced-power state.
2 . The integrated circuit as recited in claim 1 , wherein the mode of operation is a low-performance mode of operation.
3 . The integrated circuit as recited in claim 1 , wherein the mode of operation corresponds to an idle condition.
4 . The integrated circuit as recited in claim 1 , wherein responsive to the mode of operation, the control circuitry is further configured to maintain a cache of at least one of the plurality of functional blocks in a sleep state while portions of that functional block are powered down.
5 . The integrated circuit as recited in claim 4 , wherein each of the plurality of functional blocks is configured to store data in a local cache.
6 . The integrated circuit as recited in claim 1 , wherein the control circuitry is further configured to rotate among the plurality of functional blocks to determine which functional block is to be activated for servicing memory requests.
7 . The integrated circuit as recited in claim 1 , wherein the data is video frame data.
8 . A method comprising:
storing data, by a plurality of functional blocks, in an interleaved manner; and in response to a mode of operation:
causing, by control circuitry, data that is stored in two or more of the plurality of functional blocks to be transferred to a selected block of the functional blocks
such that the data is stored within the selected block in a contiguous manner; and
activating, selectively, one or more of the plurality of functional blocks to service memory requests based on servicing requirements, while placing at least one
other functional block in a reduced-power state.
9 . The method as recited in claim 8 , wherein the mode of operation is a low-performance mode of operation.
10 . The method as recited in claim 8 , wherein the mode of operation corresponds to an idle condition.
11 . The method as recited in claim 8 , wherein responsive to the mode of operation, the method further comprises maintaining, by the control circuitry, a cache of at least one of the plurality of functional blocks in a sleep state while portions of that functional block are powered down.
12 . The method as recited in claim 11 , further comprising storing data in a local cache by each of the plurality of functional blocks.
13 . The method as recited in claim 11 , further comprising communicating with an external memory by a memory interface of each of the plurality of functional blocks.
14 . The method as recited in claim 8 , wherein the data is video frame data.
15 . A computing system comprising:
a display controller;
a plurality of chiplets configured to store data in an interleaved manner; and
a power manager;
wherein responsive to a mode of operation, the power manager is configured to:
cause data that is stored in two or more of the plurality of chiplets to be transferred to a selected chiplet such that the data is stored within the
selected chiplet in a contiguous manner; and
selectively activate one or more of the plurality of chiplets to service memory requests based on servicing requirements, while placing at
least one other chiplets in a reduced-power state.
16 . The computing system as recited in claim 15 , wherein the mode of operation is a low-performance mode of operation.
17 . The computing system as recited in claim 15 , wherein the mode of operation corresponds to an idle condition.
18 . The computing system as recited in claim 15 , wherein responsive to the mode of operation, the power manager is further configured to maintain a cache of at least one of the plurality of chiplets in a sleep state while portions of that chiplet are powered down.
19 . The computing system as recited in claim 18 , wherein each of the plurality of chiplets is configured to store data in a local cache.
20 . The computing system as recited in claim 18 , wherein each of the plurality of chiplets comprises a memory interface configured to be coupled to an external memory.