IP Library › Granted Patent US 12,652,753
Granted Patent B2
US 12,652,753 · App. 18/394,194 · Granted Jun 9, 2026

Balancing loss across all ports on printed circuit board traces

Inventors: Mike Sapozhnikov (San Jose, CA); Joel Richard Goergen (Soulsbyville, CA); David Nozadze (San Jose, CA); Amendra Koul (San Francisco, CA); Upen Reddy Kareti (Union City, CA); Sayed Ashraf Mamun (San Jose, CA)
Assignee: CISCO TECHNOLOGY, INC.
H05K1/0266
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Quick Facts
Patent No.
US 12,652,753
App. No.
18/394,194
Granted
Jun 9, 2026
Kind
B2
Abstract

In some aspects, the techniques described herein relate to a printed circuit board, comprising a layer, a first trace coupled to the layer and carrying a first signal; a second trace coupled to the layer and carrying a second signal; and a loss introducing feature that creates an additional signal loss in one of the first trace or the second trace, wherein the additional signal loss balances a first signal loss and a second signal loss.

Claims (36)

1 . A printed circuit board, comprising:

a layer;

a first trace coupled to the layer and carrying a first signal, the first trace having a first end and a second end opposite the first end, the first signal in the first trace encountering a first signal loss between the first end and the second end;

a second trace coupled to the layer and carrying a second signal, the second trace having a third end and a fourth end opposite the third end, the second signal in the second trace encountering a second signal loss between the third end and the fourth end; and

a loss introducing feature that creates an additional signal loss in one of the first trace or the second trace, a sum of the additional signal loss and the one of the first trace or the second trace is approximately the same as the other of the first trace or the second trace, wherein the additional signal loss balances the first signal loss and the second signal loss.

2 . The printed circuit board of claim 1 , further comprising:

a chip;

a first panel port; and

a second panel port, wherein the first end of the first trace is connected to the chip, the second end of the first trace is connected to the first panel port, the third end of the second trace is connected to the chip, and the fourth end of the second trace is connected to the second panel port.

3 . The printed circuit board of claim 2 , wherein the additional signal loss is created in the second trace.

4 . The printed circuit board of claim 1 , wherein the first trace has a first length, the second trace has a second length, the first length being larger than the second length, and a sum of the second signal loss and the additional signal loss is substantially the same as the first signal loss.

5 . The printed circuit board of claim 1 , wherein the first signal at the second end has a first strength, the second signal at the fourth end has a second strength, and the second strength is substantially the same as the first strength.

6 . The printed circuit board of claim 1 , wherein the layer has a first portion made of a first material having a first dissipation factor and a second portion made of a second material having a second dissipation factor, and the second dissipation factor is different than the first dissipation factor.

7 . The printed circuit board of claim 6 , wherein the layer has a third portion made of the first material, and the first portion, the second portion, and the third portion are arranged as stripes across the layer.

8 . The printed circuit board of claim 7 , wherein the layer includes a plurality of indicators, each of the plurality of indicators is associated with one of the stripes, and each of the plurality of indicators indicates properties of a material of its associated stripe.

9 . The printed circuit board of claim 6 , wherein the layer has a third portion made of the first material, and a fourth portion made of the second material, and the first portion, the second portion, the third portion, and the fourth portion are arranged in a checkerboard pattern.

10 . The printed circuit board of claim 6 , wherein each of the first portion and the second portion is formed of a mixture of glass and a resin, the first material is a first resin, the second material is a second resin, and the second resin is different than the first resin.

11 . The printed circuit board of claim 1 , wherein the layer has a first portion made of a first material having a first dissipation factor and a second portion made of a second material having a second dissipation factor different than the first dissipation factor, the first trace being in contact with the first portion, the second trace being in contact with the second portion, and a strength of the first signal at the second end is substantially the same as a strength of the second signal at the fourth end.

12 . The printed circuit board of claim 11 , wherein the first trace has a first length, the second trace has a second length, and the second length is different than the first length.

13 . A printed circuit board, comprising:

a layer having a first portion and a second portion, the first portion being formed of a first material, the second portion being formed of a second material, the second material having different dissipation properties from the first material;

a first trace coupled to the layer and carrying a first signal, the first trace having a first end and a second end opposite the first end, the first trace being proximate to the first material and having a first length; and

a second trace coupled to the layer and carrying a second signal, the second trace having a third end and a fourth end opposite the third end, the second trace being proximate to the second material and having a second length, the second length being greater than the first length, wherein the first material induces a first signal loss in the first trace, the second material induces a second signal loss in the second trace, and the first material and the second material create signal losses in the first trace and in the second trace respectively such that signal losses in the first trace and in the second trace are substantially the same.

14 . The printed circuit board of claim 13 , further comprising:

a chip;

a first panel port; and

a second panel port, wherein the first end of the first trace is connected to the chip, the second end of the first trace is connected to the first panel port, the third end of the second trace is connected to the chip, and the fourth end of the second trace is connected to the second panel port, the first signal at the second end has a first strength, the second signal at the fourth end has a second strength, and the second strength is substantially the same as the first strength.

15 . The printed circuit board of claim 13 , wherein the first material has a first dissipation factor and the second material has a second dissipation factor, the second dissipation factor being different than the first dissipation factor.

16 . The printed circuit board of claim 15 , wherein the layer has a third portion made of the first material, the first portion, the second portion, and the third portion are arranged as stripes across the layer, the layer includes a plurality of indicators, each of the plurality of indicators is associated with one of the stripes, and each of the plurality of indicators indicates properties of a material of its associated stripe.

17 . The printed circuit board of claim 13 , wherein the layer has a third portion being formed of a third material, the third material having different dissipation properties from the first material and the second material, and at least one of the first portion, the second portion or the third portion includes an indicator associated therewith that denotes one of the portions of the layer.

18 . The printed circuit board of claim 13 , wherein the first trace is in contact with the first portion, the second trace is in contact with the second portion, and a strength of the first signal at the second end is substantially the same as a strength of the second signal at the fourth end.

19 . A printed circuit board, comprising:

a layer having a loss balancing feature, the loss balancing feature including a first portion of the layer being formed of a first resin material having first dissipation properties and a second portion of the layer being formed of a second resin material having second dissipation properties, the second dissipation properties being different from the first dissipation properties;

a first trace coupled to the layer and in contact with the first portion, the first trace having a first length and extending from a first end to a second end, the first trace carrying a first signal that has a first strength at the first end and a second strength at the second end; and

a second trace coupled to the layer and in contact with the second portion, the second trace having a second length and extending from a third end to a fourth end, the second trace carrying a second signal that has a third strength at the third end and a fourth strength at the fourth end, wherein the second length is greater than the first length, the first strength is substantially the same as the third strength, and the second strength is substantially the same as the fourth strength due to the loss balancing feature of the layer causing a signal loss in the first trace to be substantially the same as a signal loss in the second trace.

20 . The printed circuit board of claim 19 , wherein the loss balancing feature includes a third portion being formed of a third resin material having third dissipation properties, the third dissipation properties being different from the first and second dissipation properties, and at least one of the first portion, the second portion or the third portion includes an indicator associated therewith that that denotes one of the portions of the loss balancing feature.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2023
From: SAPOZHNIKOV, MIKE; GOERGEN, JOEL RICHARD; NOZADZE, DAVID; KOUL, AMENDRA; KARETI, UPEN REDDY; MAMUN, SAYED ASHRAF
To: CISCO TECHNOLOGY, INC.
Reel/Frame 065942/0759 →
Continuity (1)
Related Publication 20250212319A1 · Jun 26, 2025
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