Backside contacts for stacked transistor structures with shifted channels
A semiconductor structure includes a first transistor including a first set of one or more channels, a second transistor vertically stacked over the first transistor, the second transistor including a second set of one or more channels, the second set of channels of the second transistor being horizontally offset from the first set of channels of the first transistor. The semiconductor structure also includes a power plane at a first side of the semiconductor structure, and a contact extending from the first side of the semiconductor structure, through the power plane, to a source/drain region of the second transistor.
1 . A semiconductor structure, comprising:
a first transistor comprising a first set of one or more channels;
a second transistor vertically stacked over the first transistor, the second transistor comprising a second set of one or more channels, the second set of channels of the second transistor being horizontally offset from the first set of channels of the first transistor;
a power plane at a first side of the semiconductor structure; and
a contact extending from the first side of the semiconductor structure, through the power plane, to a source/drain region of the second transistor.
2 . The semiconductor structure of claim 1 , wherein the power plane is disposed in an interlayer dielectric layer at the first side of the semiconductor structure, the contact extending through the interlayer dielectric layer.
3 . The semiconductor structure of claim 2 , wherein the contact further extends through shallow trench isolation regions, another interlayer dielectric layer surrounding source/drain regions for the first transistor, and a bonding oxide disposed between the first transistor and the second transistor.
4 . The semiconductor structure of claim 1 , further comprising a dielectric liner on at least a portion of sidewalls of the contact, the dielectric liner isolating the contact from the power plane.
5 . The semiconductor structure of claim 1 , wherein the contact at least partially wraps around the source/drain region of the second transistor.
6 . The semiconductor structure of claim 1 , wherein the contact abuts an additional contact to a source/drain region of the first transistor, and further comprising a dielectric liner isolating the contact from the additional contact.
7 . The semiconductor structure of claim 6 , further comprising a first silicide liner disposed between the contact and the source/drain region of the second transistor and a second silicide liner disposed between the additional contact and the source/drain region of the first transistor, the second silicide liner comprising a different silicide material than the first silicide liner.
8 . The semiconductor structure of claim 1 , further comprising a gate isolation layer surrounding a gate stack of the first transistor, the gate isolation layer comprising a different dielectric material than a gate spacer for the gate stack of the first transistor and an interlayer dielectric layer surrounding source/drain regions of the first transistor.
9 . A semiconductor structure, comprising:
a first transistor comprising a first set of one or more channels;
a second transistor vertically stacked over the first transistor, the second transistor comprising a second set of one or more channels, the second set of channels of the second transistor being horizontally offset from the first set of channels of the first transistor;
a first backside contact to a source/drain region of the first transistor;
a second backside contact to a source/drain region of the second transistor; and
a dielectric liner separating the second backside contact from the first backside contact and the source/drain region of the first transistor.
10 . The semiconductor structure of claim 9 , wherein the second backside contact extends through a backside power plane connected to the first backside contact, the source/drain region of the first transistor, an interlayer dielectric layer surrounding the source/drain region of the first transistor, and a bonding oxide disposed between the first transistor and the second transistor.
11 . The semiconductor structure of claim 9 , further comprising a first silicide liner disposed between the first backside contact and the source/drain region of the first transistor and a second silicide liner disposed between the second backside contact and the source/drain region of the second transistor, the second silicide liner being a different silicide material than the first silicide liner.
12 . The semiconductor structure of claim 9 , wherein the second backside contact at least partially wraps around the source/drain region of the second transistor.
13 . The semiconductor structure of claim 9 , further comprising a gate isolation layer surrounding a gate stack of the first transistor, the gate isolation layer comprising a different dielectric material than a gate spacer for the gate stack of the first transistor and an interlayer dielectric layer surrounding the source/drain region of the first transistor.
14 . A stacked transistor structure comprising:
a first transistor comprising a first set of one or more channels;
a second transistor vertically stacked over the first transistor, the second transistor comprising a second set of one or more channels, the second set of channels of the second transistor being horizontally offset from the first set of channels of the first transistor;
a first backside contact to a source/drain region of the first transistor; and
a second backside contact to a source/drain region of the second transistor, the second backside contact being self-aligned to the first backside contact and the source/drain region of the first transistor.
15 . The stacked transistor structure of claim 14 , wherein the second backside contact is further self-aligned to a gate region shared by the first transistor and the second transistor.
16 . The stacked transistor structure of claim 14 , wherein the second backside contact at least partially wraps around the source/drain region of the second transistor.
17 . The stacked transistor structure of claim 14 , wherein the second backside contact is disposed through a backside interlayer dielectric layer, a backside power plane connected to the first backside contact disposed in the backside interlayer dielectric layer, another interlayer dielectric layer surrounding the source/drain region of the first transistor, and a bonding oxide disposed between the first transistor and the second transistor.
18 . A complementary field-effect transistor structure comprising:
a complementary field-effect transistor cell comprising a first transistor and a second transistor stacked vertically over the first transistor, wherein a first set of one or more channels of the first transistor are horizontally offset, within the complementary field-effect transistor cell, from a second set of one or more channels of the second transistor;
a first backside contact to a source/drain region of the first transistor; and
a second backside contact to a source/drain region of the second transistor, the second backside contact being self-aligned to the first backside contact and the source/drain region of the first transistor.
19 . The complementary field-effect transistor structure of claim 18 , wherein the second backside contact is further self-aligned to a gate region shared by the first transistor and the second transistor.
20 . The complementary field-effect transistor structure of claim 18 , wherein the second backside contact at least partially wraps around the source/drain region of the second transistor.
21 . The complementary field-effect transistor structure of claim 18 , wherein the second backside contact is disposed through a backside interlayer dielectric layer, a backside power plane connected to the first backside contact disposed in the backside interlayer dielectric layer, another interlayer dielectric layer surrounding the source/drain region of the first transistor, and a bonding oxide disposed between the first transistor and the second transistor.
22 . An integrated circuit comprising:
a stacked transistor structure comprising:
a first transistor comprising a first set of one or more channels;
a second transistor vertically stacked over the first transistor, the second transistor comprising a second set of one or more channels, the second set of channels of the second transistor being horizontally offset from the first set of channels of the first transistor;
a first backside contact to a source/drain region of the first transistor; and
a second backside contact to a source/drain region of the second transistor, the second backside contact being self-aligned to the first backside contact and the source/drain region of the first transistor.
23 . The integrated circuit of claim 22 , wherein the second backside contact is further self-aligned to a gate region shared by the first transistor and the second transistor.
24 . The integrated circuit of claim 22 , wherein the second backside contact at least partially wraps around the source/drain region of the second transistor.
25 . The integrated circuit of claim 22 , wherein the second backside contact is disposed through a backside interlayer dielectric layer, a backside power plane connected to the first backside contact disposed in the backside interlayer dielectric layer, another interlayer dielectric layer surrounding the source/drain region of the first transistor, and a bonding oxide disposed between the first transistor and the second transistor.