Granted Patent B2

US 12,656,953 · App. 18/105,539 · Granted Jun 16, 2026

Inventor: Alberto Troia (Munich, DE)

G06F3/0611G06F3/0625G06F3/0634G06F3/0656G06F3/0659G06F3/0673G06N3/04

Abstract

Claims (42)

1 . An apparatus, comprising:

a memory device including:

a number of memory arrays including a plurality of input blocks and a plurality of output blocks; and

a controller, wherein the controller is configured to:

receive a command indicating that the memory device operates in an artificial intelligence (AI) mode, wherein the command inhibits access to a number of registers associated with normal operation of the memory device and allows access to the number of registers associated with AI operations;

cause the memory device to perform AI operations using an AI accelerator based on a status of the number of registers, wherein the status of the number of registers includes a number of bits programmed to indicate information associated with performing AI operations;

cause the memory device to perform the AI operations by locating input data in the plurality of input blocks based on the status of the number of registers and sending results of the AI operations to the plurality of output blocks, wherein the number of resisters indicate a start address and an end address of the input data in the plurality of input blocks, a size of the input data, and a number of inputs in the input data;

cause the memory device to perform the AI operations by locating bias values data in the number of arrays based on the status of the number of registers and sending the bias values to the AI accelerator; and

cause the memory device to perform the AI operations by locating activation function data in the number of arrays based on the status of the number of registers and sending the activation function data to the AI accelerator.

2 . The apparatus of claim 1 , wherein the AI accelerator is configured to perform logic operations of the AI operations on the input data.

3 . The apparatus of claim 1 , wherein the controller is configured to cause the memory device to store results of the AI operations by locating the plurality of output blocks in the number of arrays based on the status of the number of registers.

4 . The apparatus of claim 1 , wherein the controller is configured to cause the memory device to perform the AI operations by locating neural network data in the number of arrays based on the status of the number of registers and sending the neural network data to the AI accelerator.

5 . The apparatus of claim 1 , wherein the controller is configured to cause the memory device to perform the AI operations by locating temporary banks in the number of arrays based on the status of the number of registers and sending the data from the AI operations to the temporary banks.

6 . The apparatus of claim 1 , wherein the AI accelerator includes an adder/multiplier to perform the AI operations.

7 . An apparatus, comprising:

a memory device including:

a number of memory arrays including a plurality of input blocks and a plurality of output blocks;

an artificial intelligence (AI) accelerator, wherein the AI accelerator includes hardware configured to perform AI operations; and

a controller configured to:

receive a command from a host to perform artificial intelligence (AI) operations using the AI accelerator, wherein the command inhibits access to a number of registers associated with normal operation of the memory device and allows access to the number of registers associated with AI operations;

cause execution of the command using the AI accelerator to perform logic operations associated with the AI operations;

cause the memory device to perform the AI operations by locating input data in the plurality of input blocks based on a status of the number of registers and sending the input data to the AI accelerator, wherein the status of the number of registers includes a number of bits programmed to indicate information associated with performing AI operations and wherein the number of resisters indicate a start address and an end address of the input data in the plurality of input blocks, a size of the input data, and a number of inputs in the input data;

cause the memory device to send results of the AI operations to the plurality of output blocks based on the status of the number of registers;

cause the memory device to perform the AI operations by locating bias values data in the number of arrays based on the status of the number of registers and sending the bias values to the AI accelerator; and

cause the memory device to perform the AI operations by locating activation function data in the number of arrays based on the status of the number of registers and sending the activation function data to the AI accelerator.

8 . The apparatus of claim 7 , wherein the controller is configured to cause sending data from the plurality of input blocks and data from a neuron block to the AI accelerator and perform a first step of the AI operations.

9 . The apparatus of claim 8 , wherein the controller is configured to cause sending a result of the first step of the AI operations to a temporary block.

10 . The apparatus of claim 9 , wherein the controller is configured to cause sending the result of the first step and data from a bias block to the AI accelerator and perform a second step of the AI operations.

11 . The apparatus of claim 10 , wherein the controller is configured to cause sending a result of the second step of the AI operations to the temporary block.

12 . The apparatus of claim 11 , wherein the controller is configured to cause sending the result of the second step and data from an activation function block to the AI accelerator and perform a third step of the AI operations.

13 . The apparatus of claim 12 , wherein the controller is configured to cause sending a result of the third step of the AI operations to the plurality of output blocks.

14 . A method, comprising:

receiving a command from a host at a memory device indicating that the memory device operates in an artificial intelligence (AI) mode, wherein the command inhibits access to a number of registers associated with normal operation of the memory device and allows access to the number of registers associated with AI operations; and

performing an artificial intelligence (AI) operation using an AI accelerator on the memory device and data stored on the memory device by:

locating input data at a plurality of input blocks on the memory device based on a status of a first register and sending the input data to the AI accelerator, wherein the status of the first register includes a number of bits programmed to indicate information associated with performing AI operations and wherein the first resister indicates a start address and an end address of the input data in the plurality of input blocks, a size of the input data, and a number of inputs in the input data;

locating bias values data in the number of arrays based on the status of the number of registers and sending the bias values to the AI accelerator;

locating activation function data in the number of arrays based on the status of the number of registers and sending the activation function data to the AI accelerator; and

sending a result of the AI operation to a plurality of output blocks on the memory device based on status of a second register.

15 . The method of claim 14 , further including performing logic operations of the AI operation using an adder/multiplier on the AI accelerator.

16 . The method of claim 14 , further including sending neuron information of a neural network to the AI accelerator to perform AI operations.

17 . The method of claim 14 , further including storing partial results of the AI operation in an array of the memory device.

18 . The method of claim 14 , further including sending activation function information of a neural network to the AI accelerator to perform AI operations.

Assignments (2)

Continuity (2)

References Cited (30)