Memory module for prefetching data, memory system including memory module, and method of operating the same
The present technology relates to an electronic device. According to the present technology, a memory system includes a host, a first memory module communicating with the host through a first interface and a second memory module communicating with the host through a second interface. The host comprises a prefetch table storage and a map manager. The prefetch table storage may store a prefetch table indicating candidate data to be prefetched to the first memory module among data stored in the second memory module. The map manager may prefetch target data from the second memory module to the first memory module according to whether the target data is included in the candidate data when the target data requested by the host is cache-missed in the first memory module and is cache-hit in the second memory module.
1 . A memory system comprising:
a host;
a first memory module communicating with the host through a first interface; and
a second memory module communicating with the host through a second interface,
wherein the host comprises:
a prefetch table storage configured to store a prefetch table indicating candidate data to be prefetched to the first memory module among data stored in the second memory module; and
a map manager configured to prefetch target data from the second memory module to the first memory module when the target data requested by the host is cache-missed in the first memory module, is cache-hit in the second memory module, and is included in the candidate data.
2 . The memory system of claim 1 , wherein the map manager determines the candidate data based on access pattern information of the host for the first memory module and a plurality of algorithms.
3 . The memory system of claim 2 , wherein the plurality of algorithms includes at least one of a temporal locality algorithm, a spatial locality algorithm, a branch locality algorithm, an equidistant locality algorithm, and a sequential locality algorithm.
4 . The memory system of claim 1 , wherein the first interface includes a dual inline memory module (DIMM) interface, and
the second interface includes a compute express link (CXL) interface.
5 . The memory system of claim 4 , wherein the second memory module has a tier lower than that of the first memory module in an access request of the host.
6 . A method of operating a memory system including a first memory module and a second memory module, the method comprising:
selecting candidate data to be prefetched to the first memory module among data stored in the second memory module based on access pattern information of a host for the first memory module and a plurality of algorithms;
determining whether target data is a cache hit in the second memory module when the target data requested by the host is a cache miss in the first memory module; and
prefetching the target data from the second memory module to the first memory module when the target data is cache-missed in the first memory module, is cache-hit in the second memory module, and is included in the candidate data.
7 . The method of claim 6 , wherein the plurality of algorithms includes at least one of a temporal locality algorithm, a spatial locality algorithm, a branch locality algorithm, an equidistant locality algorithm, and a sequential locality algorithm.
8 . The method of claim 6 , wherein the first memory module communicates with the host through a dual inline memory module (DIMM) interface, and
the second memory module communicates with the host through a compute express link (CXL) interface.
9 . The method of claim 6 , wherein the second memory module has a tier lower than that of the first memory module in the access request of the host.