Integrated circuit using multiple and different process corners
A system and method for creating layout for semiconductor chips are described. In various implementations, an integrated circuit includes at least a first functional block and a second functional block. The first functional block includes circuitry that has a first set of parameters of a first process corner. The second functional block includes circuitry that has a second set of parameters of a second process corner different from the first set of parameters of the first process corner. For a same set of operating conditions, the second functional block has device characteristics different from device characteristics of the first functional block based on the first process corner and the second process corner being different from one another. The integrated circuit is fabricated with a process corner mask that indicates which areas of the die use the first process corner and which areas use the second process corner.
1 . A semiconductor die comprising:
a first functional block on the semiconductor die, the first functional block comprising circuitry fabricated using a first set of parameters of a first process corner; and
a second functional block on the semiconductor die, the second functional block comprising circuitry fabricated using a second set of parameters of a second process corner that is different from the first process corner;
wherein for a given set of operating conditions:
the first functional block has first device characteristics based on the first set of parameters of the first process corner; and
the second functional block has second device characteristics based on the second set of parameters of the second process corner.
2 . The semiconductor die as recited in claim 1 , wherein the first functional block is fabricated using a first process flow corresponding to the first set of parameters of the first process corner, and the second functional block is fabricated using a second process flow corresponding to the second set of parameters of the second process corner.
3 . The semiconductor die as recited in claim 1 , wherein the die includes a first region containing the first functional block and a second region containing the second functional block, the first and second regions being physically distinguished by device structures formed using different respective process-corner parameter sets.
4 . The semiconductor die as recited in claim 3 , wherein the first region aligned with the first functional block is fabricated using the first set of process-corner parameters and the second region aligned with the second functional block is fabricated using the second set of process-corner parameters.
5 . The semiconductor die as recited in claim 1 , wherein the second process corner that provides the device characteristics of the second functional block comprises values different from values of the first process corner for one or more parameters that include one or more of: a carrier mobility of n-type devices, a gate oxide thickness of p-type devices, and a doping concentration of source and drain regions of n-type devices.
6 . The semiconductor die as recited in claim 1 , wherein first and second regions of the die are defined by a process-corner photomask having transparent and opaque areas respectively aligned with the first functional block and the second functional block.
7 . The semiconductor die as recited in claim 1 , wherein each of the first functional block and the second functional block is an instance of a same circuit.
8 . A method comprising:
forming, on a semiconductor die, circuitry of a first functional block of an integrated circuit, the first functional block comprising circuitry fabricated using a first set of parameters of a first process corner; and
forming, on the semiconductor die, circuitry of a second functional block different from the first functional block of the integrated circuit, the second functional block comprising circuitry fabricated using a second set of parameters of a second process corner that is different from the first process corner;
wherein for a given set of operating conditions:
the first functional block is configured to exhibit first device characteristics based on the first set of parameters of the first process corner; and
the second functional block is configured to exhibit second device characteristics based on the second set of parameters of the second process corner.
9 . The method as recited in claim 8 , wherein the second process corner that provides device characteristics of the second functional block comprises values different from values of the first process corner for one or more parameters that include one or more of: a carrier mobility of n-type devices, a gate oxide thickness of p-type devices, and a doping concentration of source and drain regions of n-type devices.
10 . The method as recited in claim 8 , further comprising:
receiving a file that includes design layers and one or more marker layers representing layout of the integrated circuit; and
reading, from the file, a marker layer of the one or more marker layers indicating which functional blocks of the integrated circuit to exclude from the first process corner.
11 . The method as recited in claim 10 , further comprising creating, based on the one or more marker layers, a photomask that is transparent in a first area of the photomask aligned with an area of the integrated circuit that comprises the first functional block.
12 . The method as recited in claim 11 , further comprising creating, based on the one or more marker layers, the photomask that is opaque in a second area of the photomask aligned with an area of the integrated circuit that comprises the second functional block.
13 . The method as recited in claim 12 , further comprising fabricating the integrated circuit using the photomask.
14 . The method as recited in claim 8 , wherein, for a given set of operating conditions, the circuitry of the first functional block has higher switching speed and higher power consumption than the circuitry of the second functional block.
15 . A computing system comprising:
a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks; and
a semiconductor die comprising:
a first functional block on a semiconductor die, the first functional block comprising circuitry fabricated using a first set of parameters of a first process corner; and
a second functional block on the semiconductor die, the second functional block comprising circuitry fabricated using a second set of parameters of a second process corner that is different from the first process corner;
wherein for a given set of operating conditions:
the first functional block has first device characteristics based on the first set of parameters of the first process corner; and
the second functional block has second device characteristics based on the second set of parameters of the second process corner.
16 . The computing system as recited in claim 15 , wherein the device characteristics comprise one or more of device switching speed.
17 . The computing system as recited in claim 15 , wherein the device characteristics comprise device leakage current.
18 . The computing system as recited in claim 15 , wherein the given set of operating conditions comprises one or more of an operating voltage, an operating clock frequency, and an active operating state.
19 . The computing system as recited in claim 15 , wherein the second process corner that provides the device characteristics of the second functional block comprises values different from values of the first process corner for one or more parameters that include one or more of: a carrier mobility of n-type devices, a gate oxide thickness of p-type devices, and a doping concentration of source and drain regions of n-type devices.
20 . The computing system as recited in claim 15 , wherein the semiconductor die includes first and second regions respectively aligned with the first and second functional blocks, the regions being structurally defined by fabrication using different process-corner parameter sets corresponding to transparent and opaque areas of a process-corner photomask used during fabrication.