Display panel
A display panel is provided. The display panel includes multiple emission circuits, multiple emission control circuits, multiple pixel circuits, and multiple emission control lines. The emission circuit receives multiple clock signals to provide multiple emission signals. The emission control circuit receives one of the emission signals and receives multiple emission control signals to provide multiple pixel emission signals based on the received emission signal and the emission control signals. The pixel circuits are arranged in an array. The emission control lines are respectively coupled to one of the emission control circuits and pixel circuits of a same color among the pixel circuits in a row to transmit a corresponding one of the pixel emission signals to the coupled pixel circuits.
1 . A display panel, comprising:
a plurality of emission circuits, receiving a plurality of clock signals to provide a plurality of emission signals;
a plurality of emission control circuits, respectively receiving a previous emission signal, one of the emission signals and receiving a plurality of emission control signals to provide a plurality of pixel emission signals based on the previous emission signal, the received emission signal and the emission control signals;
a plurality of pixel circuits, arranged in an array;
a plurality of emission control lines, respectively coupled to one of the emission control circuits and pixel circuits of a same color among the pixel circuits in a row to transmit a corresponding one of the pixel emission signals to the coupled pixel circuits,
wherein each of the emission control circuits comprises:
a first transistor, having a first terminal, a control terminal receiving a first emission control signal among the emission control signals, and a second terminal receiving the previous emission signal;
a first capacitor, coupled between the first terminal of the first transistor and a reference voltage;
a second capacitor, coupled between a corresponding one of the emission circuits and the first terminal of the first transistor;
a second transistor, having a first terminal receiving a corresponding one of the emission signals, a control terminal coupled to the first terminal of the first transistor, and a second terminal providing a first pixel emission signal among the pixel emission signals;
a third transistor, having a first terminal, a control terminal receiving a second emission control signal among the emission control signals, and a second terminal receiving the previous emission signal;
a third capacitor, coupled between the first terminal of the third transistor and the reference voltage;
a fourth capacitor, coupled between the corresponding one of the emission circuits and the first terminal of the third transistor;
a fourth transistor, having a first terminal receiving the corresponding one of the emission signals, a control terminal coupled to the first terminal of the third transistor, and a second terminal providing a second pixel emission signal among the pixel emission signals;
a fifth transistor, having a first terminal, a control terminal receiving a third emission control signal among the emission control signals, and a second terminal receiving the previous emission signal;
a fifth capacitor, coupled between the first terminal of the fifth transistor and the reference voltage;
a sixth capacitor, coupled between the corresponding one of the emission circuits and the first terminal of the fifth transistor; and
a sixth transistor, having a first terminal receiving the corresponding one of the emission signals, a control terminal coupled to the first terminal of the fifth transistor, and a second terminal providing a third pixel emission signal among the pixel emission signals.
2 . The display panel according to claim 1 , wherein the emission control signals are a low-frequency signal.
3 . The display panel according to claim 2 , wherein a number of transitions of the low-frequency signal during a single screen period is less than or equal to 1.
4 . The display panel according to claim 1 , wherein the emission control signals are a high-frequency signal.
5 . The display panel according to claim 4 , wherein a number of transitions of the high-frequency signal during a single screen period is greater than or equal to 2.
6 . The display panel according to claim 1 , further comprising a plurality of clock signal lines and a plurality of control signal lines, wherein the clock signal lines transmit the clock signals, and the control signal lines transmit the emission control signals.
7 . The display panel according to claim 1 , wherein the pixel circuits comprise a plurality of red light emitting diode pixel circuits, a plurality of green light emitting diode pixel circuits, and a plurality of blue light emitting diode pixel circuits.
8 . The display panel according to claim 1 , wherein a pulse width of at least one of the emission control signals is different from pulse widths of the other emission control signals.
9 . The display panel according to claim 1 , wherein the pixel circuits respectively comprise:
a light emitting diode, having an anode and a cathode receiving a system low voltage;
a seventh transistor, having a first terminal receiving an initial voltage, a control terminal receiving a scan signal, and a second terminal;
an eighth transistor, having a first terminal, a control terminal receiving the scan signal, and a second terminal receiving a data voltage;
a seventh capacitor, coupled between the second terminal of the seventh transistor and the first terminal of the eighth transistor;
a nineth transistor, having a first terminal receiving a system high voltage, a control terminal receiving the corresponding one of the pixel emission signals, and a second terminal coupled to the second terminal of the seventh transistor;
a tenth transistor, having a first terminal coupled to the second terminal of the seventh transistor, a control terminal coupled to the first terminal of the eighth transistor, and a second terminal; and
an eleventh transistor, having a first terminal coupled to the second terminal of the tenth transistor, a control terminal receiving the corresponding one of the pixel emission signals, and a second terminal coupled to the anode of the light emitting diode.