Memory with page buffer pass/fail circuit

1 . A memory comprising a memory cell array and a peripheral circuit, the peripheral circuit comprising:

a trigger circuit comprising:

a fail bit signal output circuit configured to:

receive a test signal in a current representation, the test signal obtained from verification of the memory; and

generate a fail bit signal according to the test signal obtained from verification of the memory, wherein the fail bit signal is a voltage representation of the test signal; and

a reference signal output circuit coupled to the fail bit signal output circuit and configured to:

receive the fail bit signal from the fail bit signal output circuit; and

output at least one reference signal at least partially based on the fail bit signal; and

a comparator coupled with the trigger circuit and configured to compare the fail bit signal with the at least one reference signal to output a verification result.

2 . The memory of claim 1 , wherein the reference signal output circuit comprises a plurality of branches and controlled switches, wherein the plurality of branches are connected in parallel and configured to output the at least one reference signal respectively, and wherein each of the branches comprising at least one controlled switch of the controlled switches.

3 . The memory of claim 2 , wherein the controlled switches are configured so that the controlled switch having received a first enable signal is switched to an ON state for making the corresponding branch conductive and provide the at least one reference signal.

4 . The memory of claim 2 , wherein the comparator comprises at least two comparators, and the reference signal output circuit comprises at least two sub output circuits, each of which comprises at least one branch and is connected to one of the at least two comparators, wherein a number of the sub output circuits is equal to that of the comparators.

5 . The memory of claim 1 , wherein the comparator has an input terminal connected to the trigger circuit and is configured to:

compare the fail bit signal with one reference signal of the at least one reference signal to output a comparison parameter;

continue the comparison with a next reference signal of the at least one reference signal if the comparison parameter indicates that the fail bit signal is larger than the one reference signal; and

stop the comparison and output the verification result if the comparison parameter indicates that the fail bit signal is smaller than or equal to the one reference signal.

6 . The memory of claim 5 , wherein the peripheral circuit further comprises a time delay circuit coupled with the comparator and configured to:

receive a plurality of second enable signals sequentially to output delay signals; and

delay a plurality of the comparison parameters output from the comparator according to the plurality of second enable signals respectively to output delayed comparison parameters.

7 . The memory of claim 6 , wherein the peripheral circuit further comprises a latch circuit comprising a plurality of latches coupled with the time delay circuit, wherein the latches are configured to store the delayed comparison parameters and a number of the latches is the same as that of the reference signals.

8 . The memory of claim 7 , wherein the latch circuit is also coupled with the trigger circuit and the latches are configured to:

convert the delayed comparison parameters into latch signals and latch the latch signals into corresponding latches; and

output a feedback signal according to the latch signals, wherein the feedback signal is configured to trigger the trigger circuit to switch the one reference signal to be compared.

9 . The memory of claim 8 , wherein the memory further comprises a code system conversion circuit coupled with the latch circuit and configured to convert the latch signals into binary codes, wherein the binary codes are configured for calculation of the verification result.

10 . The memory of claim 9 , wherein the peripheral circuit further comprises an accumulator coupled with the code system conversion circuit and configured to accumulate a plurality of the binary codes obtained from the code system conversion circuit to obtain the verification result of a fail bit count.

11 . The memory of claim 8 , wherein the latch circuit is further configured to receive a reset signal to reset the latch signals.

12 . The memory of claim 1 , wherein the peripheral circuit further comprises a reference circuit connected with the trigger circuit and configured to output a control signal to the trigger circuit based on an externally input signal, wherein the control signal is configured to enable the trigger circuit.

13 . The memory of claim 12 , wherein the control signal comprises a first control signal and a second control signal, wherein the first control signal is configured to enable the reference signal output circuit to output a plurality of the at least one reference signals, and the second control signal is configured to enable the fail bit signal output circuit to receive the test signal.

14 . A method of controlling a peripheral circuit of a memory, the method comprising:

receiving a test signal in a current representation, the test signal obtained from verification of the memory;

generating a fail bit signal according to the test signal obtained from verification of the memory, wherein the fail bit signal is a voltage representation of the test signal;

outputting at least one reference signal at least partially based on the fail bit signal;

and comparing the fail bit signal with the at least one reference signal determined at least partially based on the fail bit signal to output a verification result.

15 . The method of claim 14 , wherein the control method further comprises receiving a plurality of first enable signals sequentially, wherein a controlled switch having received a first enable signal of the plurality of first enable signals is switched to an ON state, and a branch connected with the controlled switch at the ON state is conductive and is configured to provide the at least one reference signal.

16 . The method of claim 15 , wherein comparing the fail bit signal with the at least one reference signal to output the verification result comprises:

comparing the fail bit signal with one reference signal of the at least one reference signal to output a comparison parameter;

delaying the comparison parameter according to a corresponding delay signal corresponding to the comparison parameter to output a delayed comparison parameter;

converting the delayed comparison parameter into a latch signal and latching the latch signal into a corresponding latch;

comparing the fail bit signal with a next reference signal of the at least one reference signal when the latch signal indicates that the fail bit signal is larger than the one reference signal, until the delayed comparison parameter indicates that the fail bit signal is smaller than or equal to the one reference signal;

converting the latch signals latched in a plurality of latches into binary codes respectively; and

accumulating a plurality of the binary codes to obtain and output the verification result configured to represent a fail bit count.

17 . The method of claim 16 , wherein the comparing the fail bit signal with the next reference signal when the latch signal indicates that the fail bit signal is larger than the one reference signal comprises:

outputting a feedback signal by the latch according to the latch signal; and

outputting the first enable signal to a next said controlled switch when the feedback signal indicates that the fail bit signal is larger than the one reference signal, wherein the controlled switch having received the first enable signal is turned on, and a trigger circuit generates the next reference signal which is then compared with the fail bit signal.

18 . The method of claim 16 , wherein the control method further comprises receiving a reset signal to reset the latch signals.

19 . The method of claim 16 , wherein the control method further comprises outputting a control signal based on an externally input signal, wherein the control signal comprises a first control signal configured to enable a plurality of the at least one reference signal to be output and a second control signal configured to enable the test signal to be received.

20 . A memory system, comprising:

a memory controller; and

a memory coupled to the memory controller, the memory comprising a memory cell array and a peripheral circuit, the peripheral circuit comprising:

a trigger circuit comprising:

a fail bit signal output circuit configured to:

receive a test signal in a current representation, the test signal obtained from verification of the memory; and

generate a fail bit signal according to the test signal obtained from verification of the memory, wherein the fail bit signal is a voltage representation of the test signal; and

a reference signal output circuit coupled to the fail bit signal output circuit and configured to:

receive the fail bit signal from the fail bit signal output circuit; and

output at least one reference signal at least partially based on the fail bit signal; and

a comparator coupled with the trigger circuit and configured to compare the fail bit signal with the at least one reference signal to output a verification result.