Interconnect structures for integrated circuits
Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.
1 . A semiconductor device, comprising:
an interconnect structure above a transistor above a substrate, wherein the transistor includes a gate electrode having an uppermost surface, and wherein the interconnect structure includes:
a first dielectric separation layer and a second dielectric separation layer, the second dielectric separation layer over and vertically separated from the first dielectric separation layer, and the second dielectric separation layer having a bottommost surface above an uppermost of the first dielectric separation layer;
an inter-level dielectric (ILD) material layer between the first dielectric separation layer and the second dielectric separation layer, the ILD material layer having a planar bottommost surface in contact with the first separation dielectric layer, and a planar uppermost surface in contact with the second dielectric separation layer, wherein the ILD material layer is a single material layer continuous from the planar bottommost surface to the planar uppermost surface;
a first conductor within the ILD material layer, wherein the first conductor has a first physical configuration;
a second conductor within the ILD material layer, wherein the second conductor has a second physical configuration different from the first physical configuration, wherein the second conductor has an uppermost surface at a different level than an uppermost surface of the first conductor, the uppermost surface of the first conductor and the uppermost surface of the second conductor below the planar uppermost surface of the ILD material layer and vertically spaced apart from the second dielectric separation layer, wherein the second conductor has a bottommost surface below a bottommost surface of the first conductor, the bottommost surface of the second conductor vertically overlapping with and vertically spaced apart from the planar bottommost surface of the ILD material layer and the first dielectric separation layer, and the bottommost surface of the second conductor above the uppermost surface of the gate electrode of the transistor, and wherein the uppermost surface of the second conductor is at a level below the uppermost surface and above the bottommost surface of the first conductor;
a via in the ILD material layer, the via extending from a level below the bottommost surface of the second conductor to a level above the uppermost surface of the first conductor, the via laterally spaced apart from the first conductor and the second conductor, and the via having an uppermost surface below the planar uppermost surface of the ILD material layer; and
a third conductor within the ILD material, the third conductor vertically over and coupled to the via, the third conductor having a bottommost surface above the uppermost surface of the second conductor, and the third conductor having an uppermost surface below and in contact with the bottommost surface of the second dielectric separation layer.
2 . The semiconductor device of claim 1 , wherein the first physical configuration of the first conductor includes a shape, a size, a height, or a material of the first conductor, a first depth from a first surface of the ILD material layer to the first conductor, or a second depth from a second surface of the ILD material layer to the first conductor.
3 . The semiconductor device of claim 1 , wherein the first conductor or the second conductor includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAIN, HfAIN, or InAIO.
4 . The semiconductor device of claim 1 , wherein the first conductor or the second conductor has a triangular shape, a square shape, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.
5 . The semiconductor device of claim 1 , wherein the substrate includes a silicon substrate, a glass substrate, a metal substrate, or a plastic substrate.
6 . The semiconductor device of claim 1 , wherein the ILD material layer includes silicon dioxide (SiO 2 ), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass (FSG), organic polymer, silsesquioxane, siloxane, or organosilicate glass.
7 . The semiconductor device of claim 1 , wherein the first or second dielectric separation layer includes one or more of an etching stop layer, a barrier layer, a capping layer, or a hard mask layer.
8 . The semiconductor device of claim 1 , wherein the interconnect structure further includes an interstitial bridge via within the ILD material layer.
9 . The semiconductor device of claim 8 , wherein interstitial bridge via further extends through the second dielectric separation layer into a second ILD material layer above the second dielectric separation layer.
10 . The semiconductor device of claim 1 , wherein the interconnect structure further includes a sealant layer above, below, or adjacent to the first conductor.
11 . The semiconductor device of claim 1 , wherein the first conductor is a plate of a capacitor formed within the ILD material layer, the second conductor is a contact of a transistor within the ILD material layer, and wherein the interconnect structure further includes a short via within the ILD material layer to couple the first conductor and the second conductor.