Backside programmable memory
Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.
1 . A method for forming a semiconductor device, the method comprising:
forming a front end of line structure comprising a plurality of programmable cells, each programmable cell comprising a backside via in direct contact with a device region of the respective programmable cell, wherein a first portion of the backside vias in each of the plurality of programmable cells defines one or more placeholder backside vias and a second portion of the backside vias in each of the plurality of programmable cells defines one or more programmed backside vias, wherein forming the front end of line structure comprises:
forming a backside via comprising a dielectric material in each respective programmable cell;
forming a mask over the backside vias, the mask patterned to selectively expose the second portion of the backside vias;
remove the dielectric material from the exposed second portion of the backside vias; and
replace the dielectric material with conductive material in the exposed second portion of the backside vias;
forming a back end of line structure on a first surface of the front end of line structure, the back end of line structure comprising a programmable cell control signal line; and
forming a backside structure on a second surface of the front end of line structure opposite the first surface, the backside structure comprising a backside metallization layer in direct contact with the one or more programmed backside vias, the backside metallization layer comprising a sensing signal line.
2 . The method of claim 1 , wherein the programmable cells having a placeholder backside via define a first bit value and the programmable cells having a programmed backside via define a second bit value.
3 . The method of claim 1 , wherein the one or more placeholder backside vias comprise a dielectric material and the one or more programmed backside vias comprise a conductive material.
4 . The method of claim 3 , wherein the backside metallization layer is in direct contact with the backside vias.
5 . The method of claim 1 , wherein the one or more placeholder backside vias and the one or more programmed backside vias comprise a conductive material.
6 . The method of claim 5 , wherein the one or more placeholder backside vias are recessed with respect to the one or more programmed backside vias to prevent direct contact with the backside metallization layer.
7 . The method of claim 1 , wherein the one or more programmed backside vias are selected such that a portion of the plurality of programmed cells defines a mask-programmed read-only memory (PROM).
8 . The method of claim 1 , further comprising forming a backside programmable memory cell region comprising the plurality of programmed cells and one or more additional regions intermixed with the backside programmable memory cell region.