Semiconductor device and method of manufacturing
Gate-all-around (GAA) devices and methods of manufacturing such devices are described herein. A method includes forming a multi-layer structure over a substrate and forming a plurality of source/drain regions in the multi-layer structure. Fins are then patterned into the multi-layer structure through adjacent source/drain regions. A wire release process is performed to remove materials of one or more of the layers in the multi-layer stack. The remaining layers of the multi-layer stack form a stack of nanostructures connecting adjacent source/drain regions of the fins.
1 . A semiconductor device comprising:
a gate structure, the gate structure comprising:
a gate dielectric surrounding a first nanostructure and a second nanostructure over a semiconductor substrate; and
a gate electrode surrounding the gate dielectric;
a first source/drain region in physical contact with the first nanostructure, the second nanostructure, and the gate dielectric, the first source/drain region extending into the semiconductor substrate a first distance of between about 10 nm and about 100 nm, wherein the first source/drain region has a substantially rectangular prism shape in a perspective view; and
a gate spacer on a sidewall of the gate structure, wherein a lowermost surface of the gate spacer directly contacts an uppermost surface of the first source/drain region in a cross-sectional view, wherein the cross-sectional view extends through the first nanostructure and the second nanostructure in a channel length direction.
2 . The semiconductor device of claim 1 , wherein the first source/drain region has a first width, and the first nanostructure has the first width.
3 . The semiconductor device of claim 1 , wherein the gate dielectric has a first material throughout the gate dielectric.
4 . The semiconductor device of claim 1 , wherein the first source/drain region has a first length of between about 10 nm and about 40 nm.
5 . The semiconductor device of claim 1 , wherein the first source/drain region has a first height of between about 40 nm and about 300 nm.
6 . The semiconductor device of claim 1 , further comprising:
an interlayer dielectric on opposing sides of the first source/drain region; and
a spacer layer completely separating the first source/drain region from the interlayer dielectric.
7 . The semiconductor device of claim 1 , wherein the uppermost surface of the first source/drain region is lower than a lowermost surface of the gate dielectric in the cross-sectional view.
8 . A semiconductor device comprising:
a gate structure comprising a gate dielectric and a gate electrode;
a first nanostructure over a semiconductor substrate;
a second nanostructure separated from the first nanostructure by the gate dielectric and the gate electrode, the gate electrode surrounding each of the first nanostructure and the second nanostructure;
a first source/drain region at least partially embedded within the semiconductor substrate to a distance of between about 10 nm and about 100 nm, wherein an outer perimeter of the first source/drain region in a cross-sectional view has a rectangular shape, wherein an upper surface of the first source/drain region is substantially flat, wherein the upper surface of the first source/drain region is substantially co-planar with an upper surface of the second nanostructure, wherein the cross-sectional view is substantially parallel to a longitudinal axis of the gate electrode, wherein the rectangular shape extends from a point level with a bottom of the gate electrode to a point level with the upper surface of the second nanostructure;
a second source/drain region on an opposite side of the first nanostructure and the second nanostructure from the first source/drain region, wherein the second source/drain region is in physical contact with each of the first nanostructure, the second nanostructure, and the gate dielectric; and
a gate spacer along a sidewall of the gate structure, wherein the gate spacer is directly on an uppermost surface of the first source/drain region, wherein the gate spacer is completely above the uppermost surface of the first source/drain region in a cross-sectional view, wherein the cross-sectional view extends through the first source/drain region and the second source/drain region.
9 . The semiconductor device of claim 8 , wherein the first nanostructure has a length of at least 30 nm.
10 . The semiconductor device of claim 8 , wherein the gate dielectric has a first material throughout the gate dielectric.
11 . The semiconductor device of claim 8 , further comprising a third source/drain region adjacent to the first source/drain region, the first source/drain region and the third source/drain region having a pitch of between about 40 nm and about 180 nm.
12 . The semiconductor device of claim 8 , wherein the first source/drain region has a first length of between about 10 nm and about 200 nm.
13 . The semiconductor device of claim 8 , wherein the first source/drain region has a first height of between about 24 nm and about 60 nm.
14 . The semiconductor device of claim 8 , further comprising:
a spacer layer completely covering a sidewall of the first source/drain region.
15 . A semiconductor device comprising:
a first epitaxial source/drain region;
a second epitaxial source/drain region, wherein an upper surface of the first epitaxial source/drain region is substantially co-planar with an upper surface of the second epitaxial source/drain region;
a stack of nanostructures, each nanostructure within the stack of nanostructures extending between the first epitaxial source/drain region and the second epitaxial source/drain region, wherein a first plane extends through the first epitaxial source/drain region, the second epitaxial source/drain region and the stack of nanostructures, wherein the first epitaxial source/drain region has a consistent width in a second plane for an entire height of the first epitaxial source/drain region, wherein the second plane is perpendicular to the first plane;
a gate structure comprising a gate dielectric layer and a gate electrode over the gate dielectric layer, the gate dielectric layer surrounding each nanostructure within the stack of nanostructures, wherein the gate dielectric layer is in direct physical contact with the first epitaxial source/drain region and the second epitaxial source/drain region; and
a gate spacer adjacent the gate structure, an entirety of the gate spacer being over an uppermost surface of the first epitaxial source/drain region in a cross-sectional view along a gate length direction of the gate structure.
16 . The semiconductor device of claim 15 , wherein the first epitaxial source/drain region and the second epitaxial source/drain region are silicon.
17 . The semiconductor device of claim 15 , wherein a distance between the first epitaxial source/drain region and the second epitaxial source/drain region is at least 30 nm.
18 . The semiconductor device of claim 15 , wherein the first epitaxial source/drain region has a rectangular shape in a top down view.
19 . The semiconductor device of claim 15 , wherein the stack of nanostructures has a first width and the first epitaxial source/drain region has the first width.
20 . The semiconductor device of claim 15 , further comprising:
a third epitaxial source/drain region spaced apart from the first epitaxial source/drain region;
an interlayer dielectric over and between the first epitaxial source/drain region and the third epitaxial source/drain region; and
a contact extending through the interlayer dielectric to the first epitaxial source/drain region and the third epitaxial source/drain region, wherein the interlayer dielectric contacts a bottom of the contact between the first epitaxial source/drain region and the third epitaxial source/drain region.