Semiconductor device with integrated junction field effect transistor and associated manufacturing method
A method for manufacturing a semiconductor device includes preparing a substrate of a first conductivity type having a drain region, forming a first source region and a second source region of the first conductivity type in the substrate separated from each other, and forming a gate trench of a gate region disposed closely next to or in adjoining neighbor to the first source region. The method may further include forming a first sidewall body region of a second conductivity type to separate the first source region from the second source region, forming a link region of the second conductivity type such that the link region and the gate trench are disposed spatially opposite to each other, forming a gate insulation layer to coat and line sidewalls and a bottom of the gate trench, and using a gate conductive material to fill the gate trench.
1 . A method for manufacturing a semiconductor device, comprising:
preparing a semiconductor layer of a first conductivity type having a drain region doped at least adjacent a first surface of the semiconductor layer;
forming a first portion of an epitaxial layer of the first conductivity type atop a second surface of the semiconductor layer, the second surface of the semiconductor layer being opposite to the first surface of the semiconductor layer;
forming a buried layer of the first conductivity type in or on the first portion of the epitaxial layer, wherein the buried layer has a second source dopant concentration higher than an epitaxial dopant concentration of the epitaxial layer;
forming a second portion of the epitaxial layer of the first conductivity type on the buried layer;
forming a first source region of the first conductivity type in the second portion of the epitaxial layer and adjacent a top surface of the second portion of the epitaxial layer;
forming a gate trench of a gate region in the epitaxial layer such that the gate trench is disposed closely next to or in adjoining neighbor to the first source region;
forming a first sidewall body region of a second conductivity type below or underneath the first source region to separate the first source region from the buried layer, wherein the buried layer functions as a second source region;
forming a link region of the second conductivity type such that the link region and the gate trench are respectively disposed at a first side of the first source region and a second side of the first source region, the first side of the first source region being opposite to the second side of the first source region;
forming a gate insulation layer to coat and line sidewalls and a bottom of the gate trench; and
using a gate conductive material to fill the gate trench.
2 . The method of claim 1 , wherein the drain region has a drain dopant concentration higher than the epitaxial dopant concentration of the epitaxial layer, and wherein the first source region has a first source dopant concentration higher than the epitaxial dopant concentration of the epitaxial layer.
3 . The method of claim 1 , wherein the link region has a link dopant concentration higher than the second source dopant concentration of the buried layer.
4 . The method of claim 1 , further comprising:
forming a body contact region of the second conductivity type in the second portion of the epitaxial layer adjacent the top surface of the second portion of the epitaxial layer and closely next to or in adjoining neighbor to the first source region at the first side of the first source region, wherein the body contact region has a body contact dopant concentration higher than a first body dopant concentration of the first sidewall body region.
5 . The method of claim 1 , wherein the link region has a link dopant concentration higher than a first body dopant concentration of the first sidewall body region.
6 . The method of claim 1 , wherein forming the first sidewall body region includes implanting dopants of the second conductivity type into the second portion of the epitaxial layer before forming the first source region.
7 . The method of claim 1 , further comprising:
performing an oxidation process to oxidize an uppermost portion of the gate conductive material in the gate trench to form a gate capping layer, wherein the gate capping layer has a predetermined capping thickness thicker than a predetermined gate insulation thickness of the gate insulation layer.
8 . The method of claim 1 , wherein the first source region, the first sidewall body region, and the second source region are vertically arranged along a first sidewall of the gate region.
9 . The method of claim 1 , wherein forming the first sidewall body region includes implanting dopants of the second conductivity type into the second portion of the epitaxial layer with a first predetermined angle with reference to the top surface of the second portion of the epitaxial layer through a first sidewall of the gate trench.
10 . The method of claim 1 , wherein the link region is formed to extend vertically down through the buried layer into the first portion of the epitaxial layer.
11 . The method of claim 1 , wherein the link region is formed to extend vertically down along a second sidewall of a neighboring gate region until wrapping a second bottom corner of the neighboring gate region.
12 . The method of claim 1 , wherein forming the link region includes implanting dopants of the second conductivity type into the epitaxial layer with a second predetermined angle with reference to the top surface of the second portion of the epitaxial layer through a second sidewall of a gate trench of a neighboring gate region.
13 . The method of claim 1 , further comprising:
forming a lightly doped region of the second conductivity type in the second portion of the epitaxial layer before forming the first source region.
14 . The method of claim 13 , wherein forming the first sidewall body region includes implanting dopants of the second conductivity type in the lightly doped region, and wherein the lightly doped region laterally extends beyond the first sidewall body region.
15 . The method of claim 1 , further comprising:
forming a second sidewall body region of the second conductivity type below or underneath the buried layer, wherein the link region is separated from the second sidewall body region.
16 . The method of claim 15 , wherein forming the second sidewall body region includes implanting dopants of the second conductivity type into the first portion of the epitaxial layer with a first predetermined angle with reference to the second surface of the substrate through a first sidewall of the gate trench.
17 . The method of claim 15 , wherein the second sidewall body region extends from a bottom surface of the buried layer vertically down along a first sidewall of the gate region until wrapping a first bottom corner of the gate region.
18 . The method of claim 1 , further comprising:
forming a JFET channel implantation region of the first conductivity type along and in conformal with the link region.
19 . The method of claim 1 , further comprising:
forming a guard region of the second conductivity type below or under the bottom of the gate trench, wherein the guard region has a guard region dopant concentration higher than a first body dopant concentration of the first sidewall body region.
20 . The method of claim 1 , further comprising:
forming a thick bottom oxide layer at the bottom of the gate trench after forming the gate insulation layer and before applying the gate conductive material to fill the gate trench.