Manufacturing method for reducing surface step of a passivation layer
A display device according to an embodiment includes: a substrate; a transistor that is disposed on the substrate; a light emitting diode that is disposed on the substrate, and connected to the transistor; and a passivation layer that is disposed between the transistor and the light emitting diode, wherein a surface step of the passivation layer is within a range of and including 1 nm to 30 nm.
1 . A method of manufacturing a display device, comprising:
forming a transistor on a substrate;
stacking a passivation layer that includes a first surface step on the transistor;
forming the passivation layer having an opening and a second surface step by performing exposure with an exposure mask having a first region, a second region, and a third region, each having a different light transmittance;
forming the passivation layer having a third surface step by polishing the exposed passivation layer with a planarization device; and
forming a light emitting diode that is connected with the transistor through the opening of the passivation layer.
2 . The manufacturing method of claim 1 , wherein
the first region of the exposure mask is a transmissive region where light is transmitted, the second region is a transflective region where light is partially transmitted, and the third region is a light blocking area that blocks light,
the first region is disposed to be overlapped with the opening of the passivation layer, and
the second region is disposed to be overlapped with a source electrode and a drain electrode of the transistor.
3 . The manufacturing method of the display device of claim 2 , wherein the manufacturing the transistor comprises:
forming a polycrystalline semiconductor on the substrate;
forming a first gate insulating layer on the polycrystalline semiconductor;
forming a driving gate electrode on the first gate insulating layer;
forming a second gate insulating layer on the driving gate electrode;
forming a first interlayer insulating layer on the second gate insulating layer;
forming an oxide semiconductor layer on the first interlayer insulating layer;
forming a third gate insulating layer on the oxide semiconductor;
forming a switching gate electrode on the third gate insulating layer;
forming a second interlayer insulating layer on the switching gate electrode; and
forming a first source electrode and a first drain electrode connected with the oxide semiconductor, and a second source electrode and a second drain electrode connected to the polycrystalline semiconductor on the second interlayer insulating layer,
wherein the second region is disposed to be overlapped with the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.
4 . The manufacturing method of the display device of claim 2 , wherein the forming of the transistor comprises:
forming a polycrystalline semiconductor on the substrate;
forming a gate insulating layer on the polycrystalline semiconductor;
forming a gate electrode on the gate insulating layer;
forming an interlayer insulating layer on the gate electrode; and
forming the source electrode and the drain electrode disposed on the interlayer insulation layer and connected to the polycrystalline semiconductor.
5 . The manufacturing method of the display device of claim 4 , further comprising:
forming a touch portion on the light emitting diode; and
forming an anti-reflection portion on the touch portion.
6 . The manufacturing method of the display device of claim 5 , wherein the forming of the anti-reflection portion comprises:
forming a blocking layer on the touch portion; and
forming a color filter disposed in an opening of the blocking layer.
7 . The manufacturing method of the display device of claim 6 , further comprising forming a thin film encapsulation layer between the light emitting diode and the touch portion.
8 . The manufacturing method of the display device of claim 1 , wherein the first surface step is formed to be about 300 nm to about 700 nm.
9 . The manufacturing method of the display device of claim 1 , wherein the second surface step is formed to be about 60 nm to about 90 nm.
10 . The manufacturing method of the display device of claim 9 , wherein the third surface step of the passivation layer is formed to be within a range of and including 1 nm to 30 nm.
11 . The manufacturing method of the display device of claim 1 , wherein the passivation layer comprises a first portion overlapping a source electrode and a drain electrode of the transistor and a second portion that does not overlap the source electrode and the drain electrode,
a surface height of the first portion is higher than a surface height of the second portion, and
the first portion of the passivation layer is exposed through the exposure, and polished during the polishing.