Package with improved heat dissipation efficiency and method for forming the same

1 . A package comprising:

an integrated circuit device attached to a substrate;

an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with a top surface of the integrated circuit device; and

a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure comprises:

a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer comprises a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view;

a plurality of pillars disposed over the islands of the spreading layer; and

nanostructures disposed over the pillars.

2 . The package of claim 1 , wherein the islands of the spreading layer have a height smaller than a width or a length of the islands of the spreading layer, wherein the pillars have a thickness greater than a width or a length of the pillars.

3 . The package of claim 1 , wherein a first group of the islands comprises a first portion of the islands, and a second group of the islands comprises a second portion of the islands, wherein the first portion of the islands and the second portion of the islands are staggered in the first direction.

4 . The package of claim 1 , wherein the heat dissipation structure further comprises a metal layer disposed over the integrated circuit device and the encapsulant and below the spreading layer, wherein the metal layer comprises TiNiCu, AlNiVCu, or a combination thereof.

5 . The package of claim 1 , wherein a total area of top surfaces of the pillars is over 50% of a total area of top surfaces of the integrated circuit device and the encapsulant.

6 . The package of claim 1 , wherein the pillars comprise a bulk material and nano-pores in the bulk material of the pillars.

7 . The package of claim 1 , wherein the nanostructures are nanowires erected over the pillars.

8 . The package of claim 1 , wherein the nanostructures comprise Cu, CuO, Ni, or a combination thereof.

9 . The package of claim 1 , wherein the outermost pillar of the pillars has a distance ranging from 50 um to 500 um to an edge of the encapsulant.

10 . The package of claim 1 , further comprising a ring structure laterally surrounding the encapsulant and the heat dissipation structure, wherein a top surface of the ring structure is higher than a top surface of the heat dissipation structure.

11 . A package comprising:

an integrated circuit device attached to an interposer, wherein the integrated circuit device comprises a first heat dissipation structure attached to an integrated circuit die;

an encapsulant disposed over the interposer and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with a top surface of the integrated circuit device; and

a second heat dissipation structure in physical contact with the first heat dissipation structure of the integrated circuit device and the encapsulant, wherein the second heat dissipation structure comprises:

a first island and a second island disposed over the encapsulant and the integrated circuit device;

a first pillar disposed over the first island, wherein the first pillar has a thickness greater than a width of the first pillar in a first direction; and

a second pillar disposed over the first island, wherein the second pillar has a thickness greater than a width of the second pillar in the first direction, wherein each of the first pillar and the second pillar has a bulk material and nano-pores in the bulk material.

12 . The package of claim 11 , wherein the second heat dissipation structure further comprises nanostructures disposed over the first pillar and the second pillar.

13 . The package of claim 11 , wherein the first pillar and the second pillar have different thicknesses.

14 . The package of claim 11 , wherein the first island and the second island are aligned in the first direction and partially staggered in a second direction perpendicular to the first direction.

15 . The package of claim 11 , wherein the first island and the second island are aligned in a second direction perpendicular to the first direction and partially staggered in the first direction.

16 . A package comprising:

a device layer over an interposer, wherein the device layer includes one or more integrated circuit dies and an encapsulant disposed over the interposer and laterally around the one or more integrated circuit dies;

a first island disposed over the device layer;

a second island disposed over the device layer, the first island being spaced apart from the second island;

a first pillar disposed over the first island;

a second pillar disposed over the first island, wherein each of the first pillar and the second pillar has a bulk material and pores in the bulk material;

first nanostructures disposed over the first pillar; and

second nanostructures disposed over the second pillar.

17 . The package of claim 16 , wherein the first pillar has a thickness greater than a width of the first pillar in a first direction, and wherein the second pillar has a thickness greater than a width of the second pillar in the first direction.

18 . The package of claim 16 , wherein the one or more integrated circuit dies include a first integrated circuit die, wherein the package further comprises:

a first heat dissipation structure attached to the first integrated circuit die, wherein a top surface of the encapsulant is coplanar with a top surface of the first heat dissipation structure.

19 . The package of claim 16 , wherein the first pillar and the second pillar have different thicknesses.

20 . The package of claim 16 , wherein the one or more integrated circuit dies include a first integrated circuit die, wherein the first island overlaps an interface between the first integrated circuit die and the encapsulant.