Reinforced substrates to mitigate underflow stress and package warp and methods of making the same

1 . A structure, comprising:

a package substrate comprising a core portion comprising a first material having a first bulk modulus and a first coefficient of thermal expansion and further comprising a reinforcing portion comprising a second material having a second bulk modulus and a second coefficient of thermal expansion, wherein the second bulk modulus is greater than the first bulk modulus and the second coefficient of thermal expansion is less than the first coefficient of thermal expansion, wherein a top surface of the reinforcing portion is coplanar with a top surface of the core portion and a bottom surface of the reinforcing portion is coplanar with a bottom surface of the core portion; and

an external reinforcing member located on a surface of the package substrate and having an areal overlap with the reinforcing portion of the package substrate in a plan view.

2 . The structure of claim 1 , further comprising a semiconductor die attached to the core portion of the package substrate, wherein the reinforcing portion comprises four components each respectively located proximate to a respective corner of the package substrate and the four components are located outside an area of the semiconductor die in the plan view.

3 . The structure of claim 1 , further comprising a semiconductor die that is bonded to the center portion, wherein the external reinforcing member is located entirely outside an area of the semiconductor die in the plan view.

4 . The structure of claim 3 , further comprising an underfill material portion disposed between the semiconductor die and the package substrate, where in the external reinforcing member is located entirely outside an area of the underfill material portion in the plan view.

5 . The structure of claim 4 , wherein the external reinforcing member is located above a horizontal plane including a bottom surface of the underfill material portion.

6 . The structure of claim 3 , wherein the reinforcing portion is located within a cavity located in the core portion, and the reinforcing portion is located entirely outside the area of the semiconductor die in the plan view.

7 . The structure of claim 3 , wherein the external reinforcing member comprises a ring-shaped structure surrounding the area of the semiconductor die and located outside the area of the semiconductor die in the plan view.

8 . A semiconductor package, comprising:

a package substrate comprising a core portion comprising a first material and further comprising a reinforcing portion comprising a second material, wherein a top surface of the reinforcing portion is coplanar with a top surface of the core portion and a bottom surface of the reinforcing portion is coplanar with a bottom surface of the core portion;

a semiconductor die attached to, and electrically coupled to, the package substrate; and

an external reinforcing member located on a surface of the package substrate and having an areal overlap with the reinforcing portion of the package substrate in a plan view, wherein:

the core portion comprises a fiber-reinforced polymer material; and

the reinforcing portion comprises silicon, silicon nitride, or a ceramic material.

9 . The semiconductor package of claim 8 , wherein the package substrate has a rectangular geometry, and the reinforcing portion comprises four components each respectively located proximate to a respective corner of the package substrate and located outside the area of the semiconductor die in the plan view.

10 . The semiconductor package of claim 9 , wherein the four components each have a one of a rectangular shape, a circular shape, a triangular shape, and a polygon shape.

11 . The semiconductor package of claim 8 , wherein:

the first material has a first bulk modulus and a first coefficient of thermal expansion;

the second material has a second bulk modulus that is greater than the first bulk modulus and a second coefficient of thermal expansion that is less than the first coefficient of thermal expansion; and

the second bulk modulus is greater than 100 GPa and the second coefficient of thermal expansion is less than 10 ppm/C.

12 . The semiconductor package of claim 8 , wherein the external reinforcing member is located entirely outside an area of the semiconductor die in the plan view.

13 . The semiconductor package of claim 8 , further comprising an underfill material portion disposed between the semiconductor die and the package substrate, wherein the external reinforcing member is located entirely outside an area of the underfill material portion in the plan view.

14 . The semiconductor package of claim 8 , further comprising an interposer located between the semiconductor die and the package substrate, wherein the semiconductor die is electrically coupled to the package substrate through the interposer.

15 . A method of forming a semiconductor structure, comprising:

forming a package substrate by performing operations comprising:

providing a core portion comprising a first material having a first bulk modulus and first coefficient of thermal expansion;

forming a cavity in the core portion; and

securing a reinforcing portion comprising a second material within the cavity of the core portion,

wherein the second material has a second bulk modulus that is greater than the first bulk modulus and a second coefficient of thermal expansion that is less than the first coefficient of thermal expansion, and

wherein a top surface of the reinforcing portion is coplanar with a top surface of the core portion and a bottom surface of the reinforcing portion is coplanar with a bottom surface of the core portion;

attaching a semiconductor die to the package substrate; and

forming an external reinforcing member on a surface of the package substrate such that the external reinforcing member has an areal overlap with the reinforcing portion in a plan view and does not overlap with the semiconductor die in the plan view.

16 . The method of claim 15 , further comprising:

forming an electrical interconnect layer over one or both of the core portion and the reinforcing portion; and

electrically connecting a semiconductor device to the package substrate such that the semiconductor device is electrically connected to the electrical interconnect layer.

17 . The method of claim 15 , wherein forming the package substrate further comprises:

forming the core portion as a rectangular-shaped structure;

forming four cavities in the core portion located proximate to respective four corners of the core portion;

forming the reinforcing portion as four components; and

securing the four components to the respective four cavities of the core portion.

18 . The method of claim 15 , further comprising:

forming the core portion as a first structure comprising a fiber-reinforced polymer material; and

forming the reinforcing portion as a second structure comprising silicon, silicon nitride, or a ceramic material.

19 . The method of claim 15 , further comprising applying an underfill material portion between the package substrate and the semiconductor die, wherein the external reinforcing member is formed above a horizontal plane including a bottom surface of the underfill material portion.

20 . The method of claim 15 , the reinforcing portion comprises four components each respectively located proximate to a respective corner of the package substrate.