IP Library › Granted Patent US 12,666,726
Granted Patent B2
US 12,666,726 · App. 18/384,948 · Granted Jun 23, 2026

Deep trench isolation structures for a single-photon avalanche diode

Inventors: Ping Zheng (Singapore, SG); Eng Huat Toh (Singapore, SG); Kiok Boone Elgin Quek (Singapore, SG)
Assignee: GlobalFoundries Singapore Pte. Ltd.
H10F30/225H10F71/121H10F77/14
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Quick Facts
Patent No.
US 12,666,726
App. No.
18/384,948
Filed
Oct 30, 2023
Granted
Jun 23, 2026
Kind
B2
Examiner
ANYA, IGWE U
Art Unit
2891
USPC
257/186
Abstract

Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure comprises a semiconductor layer on a top surface of a semiconductor substrate, a light-absorbing layer on a first portion of the semiconductor layer, a dielectric layer on a second portion of the semiconductor layer, and a doped region in the semiconductor substrate adjacent to the semiconductor layer. The structure further comprises a deep trench isolation structure that penetrates through the dielectric layer and the second portion of the semiconductor layer to the doped region. The deep trench isolation structure includes a conductor layer and a dielectric liner, the dielectric liner includes a portion between the conductor layer and the semiconductor layer, and the conductor layer is connected to the first doped region.

Claims (39)

1 . A structure for a single-photon avalanche diode, the structure comprising:

a semiconductor substrate having a top surface;

a semiconductor layer on the top surface of the semiconductor substrate;

a light-absorbing layer on a first portion of the semiconductor layer;

a dielectric layer on a second portion of the semiconductor layer;

a first doped region in the semiconductor substrate adjacent to the semiconductor layer; and

a deep trench isolation structure that penetrates through the dielectric layer and the second portion of the semiconductor layer to the first doped region, the deep trench isolation structure including a conductor layer and a dielectric liner, the dielectric liner including a first portion between the conductor layer and the semiconductor layer, and the conductor layer connected to the first doped region.

2 . The structure of claim 1 wherein the conductor layer of the deep trench isolation structure has a top surface, the light-absorbing layer has a top surface, and the top surface of the conductor layer is substantially coplanar with the top surface of the light-absorbing layer.

3 . The structure of claim 2 wherein the dielectric layer has a top surface, and the top surface of the dielectric layer is substantially coplanar with the top surface of the light-absorbing layer.

4 . The structure of claim 1 wherein the dielectric layer has a top surface, and further comprising:

an interlayer dielectric layer on the top surface of the dielectric layer;

a first contact that penetrates through the interlayer dielectric layer to the conductor layer; and

a second contact that penetrates through the interlayer dielectric layer to the light-absorbing layer.

5 . The structure of claim 4 wherein the first contact is disposed fully above the top surface of the dielectric layer.

6 . The structure of claim 4 wherein the first contact has a first height, and the second contact has a second height that is substantially equal to the first height.

7 . The structure of claim 6 wherein the interlayer dielectric layer has a thickness, and the first height is equal to the thickness.

8 . The structure of claim 6 wherein the interlayer dielectric layer has a thickness, and the second height is substantially equal to the thickness.

9 . The structure of claim 4 further comprising:

a second doped region having a first portion in the light-absorbing layer,

wherein the second contact is coupled to the second doped region, the first doped region is a cathode of the single-photon avalanche diode, and the second doped region is an anode of the single-photon avalanche diode.

10 . The structure of claim 9 wherein the light-absorbing layer comprises a first material, and further comprising:

a cap layer on the light-absorbing layer, the cap layer comprising a second material different from the first material,

wherein the second doped region has a second portion in the cap layer, and the second contact adjoins the cap layer.

11 . The structure of claim 4 further comprising:

a silicide layer on the conductor layer of the deep trench isolation structure, the silicide layer disposed between the first contact and the conductor layer.

12 . The structure of claim 1 wherein the deep trench isolation structure includes a first portion that fully surrounds the light-absorbing layer.

13 . The structure of claim 12 wherein the deep trench isolation structure includes a second portion that fully surrounds the first portion and the second portion of the semiconductor layer.

14 . The structure of claim 1 wherein the deep trench isolation structure includes a trench that extends through the conductor layer and the dielectric layer to a portion of the first doped region, and the conductor layer is disposed inside the trench.

15 . The structure of claim 1 wherein the dielectric liner includes a second portion disposed between the conductor layer and the dielectric layer.

16 . The structure of claim 1 wherein the dielectric layer has a top surface, and the deep trench isolation structure is positioned between the top surface of the semiconductor substrate and the top surface of the dielectric layer.

17 . The structure of claim 1 wherein the semiconductor layer has a first thickness, the dielectric layer has a second thickness, and the deep trench isolation structure has a height that is substantially equal to a sum of the first thickness and the second thickness.

18 . The structure of claim 1 wherein the light-absorbing layer comprises a semiconductor material.

19 . The structure of claim 1 wherein the conductor layer comprises doped polysilicon, metal, or a combination of doped polysilicon and metal.

20 . A method of forming a structure for a single-photon avalanche diode, the method comprising:

forming a semiconductor layer on a top surface of a semiconductor substrate;

forming a light-absorbing layer on a first portion of the semiconductor layer;

forming a dielectric layer on a second portion of the semiconductor layer;

forming a doped region in the semiconductor substrate adjacent to the semiconductor layer; and

forming a deep trench isolation structure that penetrates through the dielectric layer and the second portion of the semiconductor layer to the doped region, wherein the deep trench isolation structure includes a conductor layer and a dielectric liner including a portion between the conductor layer and the semiconductor layer, and the conductor layer is connected to the doped region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2023
From: ZHENG, PING; TOH, ENG HUAT; QUEK, KIOK BOONE ELGIN
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 065386/0202 →
Continuity (1)
Related Publication 20250142984A1 · May 1, 2025
References Cited (6)
US 11784196B2 · Zheng et al. · 2023 [cited by applicant]
US 20220359580A1 · Zheng · 2022 [cited by examiner]
US 20230065063A1 · Zheng · 2023 [cited by examiner]
US 20230131505A1 · Linardy · 2023 [cited by examiner]
Vines, Peter et al., “High performance planar germanium-on-silicon single-photon avalanche diode detectors.” Nature Communications. 10. 1086. 10.1038/s41467-019-08830-w. (2019). [cited by applicant]
Zheng, Ping et al., “Trenchless Single-Photon Avalanche Diodes” filed on Aug. 22, 2023 as a U.S. Appl. No. 18/236,484. [cited by applicant]