IP Library › Granted Patent US 12,666,959
Granted Patent B2
US 12,666,959 · App. 18/150,184 · Granted Jun 23, 2026

Method for forming semiconductor structure including capacitor

Inventors: Min-Feng Kao (Chiayi City, TW); Dun-Nian Yaung (Taipei City, TW); Hsing-Chih Lin (Tainan City, TW); Jen-Cheng Liu (Hsin-Chu City, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H10W20/496H10F39/018H10F39/809H10W80/312H10W80/327H10W90/792
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Quick Facts
Patent No.
US 12,666,959
App. No.
18/150,184
Granted
Jun 23, 2026
Kind
B2
Abstract

A semiconductor structure is provided. The semiconductor structure includes a first die and a second die. The first die includes a substrate, an interconnection structure and a capacitor structure. The substrate has a front-side surface and a back-side surface. The interconnection structure is disposed over the front-side surface. The capacitor structure extends from the back-side surface to the front-side surface and into the interconnection structure. The second die is disposed over the back-side surface and is bonded to the first die. A method for forming a semiconductor structure is also provided.

Claims (35)

1 . A method for forming a semiconductor structure, comprising:

receiving a first die having a first semiconductor substrate and a first interconnection structure over the first semiconductor substrate, wherein the first semiconductor substrate has a first front-side surface and a first back-side surface, and at least a transistor is formed in the first semiconductor substrate on the first front-side surface;

forming a trench penetrating through the first back-side surface and the first front-side surface, wherein the trench exposes a portion of the first interconnection structure;

forming a capacitor structure in the trench; and

bonding a second die to the first die, wherein the second die comprises a second substrate and a second interconnection structure, and the capacitor structure is separated from the second interconnection structure,

wherein the capacitor structure has a first surface coupled to the first interconnection structure and a second surface opposite to the first surface, and a width of the first surface is less than a width of the second surface.

2 . The method of claim 1 , wherein the trench exposes a metal feature in the first interconnection structure.

3 . The method of claim 1 , further comprising forming a liner in the trench lining a sidewall of the first substrate prior to forming the capacitor structure in the trench.

4 . A method for forming a semiconductor structure, comprising:

receiving a first die having a first substrate and a first interconnection structure over the first substrate, wherein the first substrate has a front-side surface and a back-side surface;

bonding a second die to the first die, wherein the second die comprises a second substrate and a second interconnection structure over the second substrate, wherein the first interconnection structure and the second interconnection structure are disposed between the first substrate and the second substrate;

forming a first trench in the first substrate penetrating through the back-side surface and front-side surface after the bonding of the second die to the first die, wherein the first trench exposes a portion of the first interconnection structure; and

forming a capacitor structure in the first trench, wherein the capacitor structure is separated from the second interconnection structure, and the capacitor structure has a first surface coupled to the first interconnection structure and a second surface opposite to the first surface, and a width of the first surface is less than a width of the second surface.

5 . The method of claim 4 , further comprising forming a dielectric layer over the back-side surface of the first substrate prior to the forming of the first trench.

6 . The method of claim 4 , wherein the first trench exposes a metal feature in the first interconnection structure.

7 . The method of claim 6 , wherein the metal feature comprises a multiple level metal lines.

8 . The method of claim 4 , further comprising forming a liner in the first trench lining a sidewall of the first substrate prior to forming the capacitor structure in the first trench.

9 . The method of claim 4 , wherein the first substrate further comprises a first bonding structure, the second substrate further comprises a second bonding structure, and the first bonding structure is bonded to the second bonding structure.

10 . The method of claim 4 , further comprising:

forming a second trench in the first substrate penetrating through the back-side surface and front-side surface, wherein the second trench is separated from the capacitor structure; and

forming a through-substrate via (TSV) in the second trench.

11 . The method of claim 10 , wherein the second trench exposes a metal feature in the first interconnection structure.

12 . The method of claim 10 , further comprising forming a liner in the second trench lining a sidewall of the first substrate prior to forming the TSV in the second trench.

13 . The method of claim 4 , further comprising forming an image sensor structure over the second substrate, wherein the second substrate is disposed between the image sensor structure and the second interconnection structure.

14 . A method for forming a semiconductor structure, comprising:

receiving a first die having a first semiconductor substrate and a first interconnection structure over the first semiconductor substrate, wherein the first semiconductor substrate has a front-side surface and a back-side surface, and at least a transistor is formed in the first semiconductor substrate on the front-side surface;

forming a trench penetrating through the back-side surface and the front-side surface, wherein the trench exposes a portion of the first interconnection structure;

forming a capacitor structure in the trench, wherein the capacitor structure has a first surface facing the first interconnection structure and a second surface opposite to the first surface, and the first surface is lower a top surface of the first interconnection structure, and a width of the first surface is less than a width of the second surface; and

bonding a second die to the first die, wherein the second die comprises a second substrate and a second interconnection structure over the second substrate, wherein the first semiconductor substrate and the second interconnection structure are disposed between the first interconnection structure and the second substrate.

15 . The method of claim 14 , further comprising forming a first bonding structure over the capacitor structure, wherein the first bonding structure is bonded to a second bonding structure of the second die.

16 . The method of claim 14 , further comprising forming a TSV in the first die, wherein the TSV penetrates through the back-side surface and the front-side surface, and is separated from the capacitor structure.

17 . The method of claim 16 , further comprising forming a first bonding structure over the TSV and the capacitor structure, wherein the first bonding structure is bonded to a second bonding structure of the second die.

18 . The method of claim 16 , wherein the forming of the TSV is performed after the forming of the capacitor structure.

19 . The method of claim 14 , further comprising bonding a third die to the first die prior to the forming of the trench.

20 . The method of claim 19 , further comprising forming an image sensor structure over the third die after the bonding of the second die to the first die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2023
From: KAO, MIN-FENG; YAUNG, DUN-NIAN; LIN, HSING-CHIH; LIU, JEN-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 062277/0209 →
Continuity (1)
Related Publication 20240222261A1 · Jul 4, 2024
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